This paper studies the problem of reconstructing a planar surface from stereo images of multiple feature points that are known to be coplanar in the scene. We present a direct method by applying maximum likelihood estimation based on a statistical model of image noise. The significant fact about our method is that not only the 3-D position of the surface is reconstructed accurately but its reliability is also computed quantitatively. The effectiveness of our method is demonstrated by doing numerical simulation.

The goal of this paper is to propose a new symbolic model checking approach named time-space modal model checking, which could be applicable to verification of bit-slice microprocessor of infinite bit width and one dimensional systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.

As microprocessor units have become faster, DRAMs have also been required to become faster. One of the fast DRAMs is the synchronous DRAM, which transfers data at a high rate. We have developed a 100-MHz Synchronous DRAM using pipeline architecture and new high speed I/O lines method. This paper describes some features of the DRAM and its new pipeline architecture.

Retiming is a technique to resynthesize a synchronous sequential circuit by rearranging flip-flops. In view of logic optimization, retiming can potentially derive a circuit which is more simplified and testable because retiming can convert several sequential redundancies into combinational redundancies. Retiming methods proposed before have no guarantee to generate the same output sequences when the circuit start from a specified initial state such as the reset state. If the circuit with a specified initial state must have the same output sequences after retiming, rearrangement of flip-flops should be restricted. This paper presents a retiming method for circuits with a specified initial state so that retimed circuits give the same output sequences of the original circuits for any input sequences. In the proposed method, during the procedure of retiming each flip-flop keeps a value corresponding to the initial state and unification of flip-flops with different value is avoided. Our procedures uses 5-valued logic on gate level implementation to describe and calculate the values of flip-flops. Therefore after optimization using our method, the circuit has completely the same behavior as that of the original. Experimental results for ISCAS'89 benchmark circuits show the method can be used to optimize the circuits as well as a method without considering the initial state. And testability of the retimed circuit is more enhanced than that of the original circuit.

The firing squad synchronization problem is considered for defective cellular automata. A lower bound of time tf for the problem is derived. The state complexity to solve the problem is investigated and it is shown that the state set has to be arbitrary large to obtain solutions of time complexity (n). For memory-augmented defective cellular automata a tf-time solution is given.

In the course of the development of the "Hyper Hospital," a novel medical care system constructed in the computerized information network using virtual reality as its human interface, we devised a virtual reality world creating system which allows users to con figure the world interactively. The re-configuration of the virtual world was designed to be carried out without interruptions of activity and the world can continue to exist during the reconfiguration process. This facility comprises an important part of our Hyper Hospital system because one of our major goals of this proposal of the Hyper Hospital is to restore maximum freedom for patients in the medical care system. Discussion was given in the present study with respect to the basic requirements of the system to be realized, including discussions on the permission given to the participants of different levels, and means by which to modify the structure of the virtual world. A preliminary implementation was described following this general consideration. The developed prototype was shown to be practically suitable to the test of our virtual environment applied to realistic medical scenes.

There is general trend toward larger chip size and tighter layout due to customer requests of loading more and more functions on single chip. This trend makes yield difficult to be maintained high enough, since larger amount of defects are distributed on such large and tight-ruled chips. To overcome such a situation, RADLYS (RAnDom Logic Yield Simulator) and DD-TEG (Defect Density TEG) have been developed. DD-TEG extracts defect size distribution and its amount automatically, while RADLYS simulates defects on any layout and outputs yield based on the extracted defect size distribution. Critical layout from yield point of view can be found in this procedure. DD-TEG and RADLYS are used as a set of parameter extraction and simulation of the SPICE. In this paper, we introduce these tools and showed two application results. The predicted yield showed a good agreement with the actual yield in the first application (Optical Device A). Critical layout at the Local I/O portion was found in the second application (Random Logic portion of Memory Device B) and the layout was changed based on the RADLYS results.

We consider slotted ALOHA systems with a controlled output power level. The systems were proposed to improve the throughput performance by the capture effect. However widely used linear modulation systems have no capture effect, and a power level distribution dominates the performance in those systems. In this paper we consider linear modulation systems employing PSK. We introduce an average error probability of the highest power signal as a performance measure, and a uniform distribution is applied to the error probability analysis. Numerical results show the superiority of the systems with uniform distribution to a conventional slotted ALOHA in a heavy traffic condition. On the other hand, in a light traffic condition, the optimal power distribution which minimizes the error probability is obtained for 2-level ALOHA. We also propose the power level selection method to search the optimal power level. The validity of analytical results are confirmed by simulations.

The subject is the horizontal coil's temperature rise in DY for high frequency by being unavoidable for the tendency of more information on display monitor equipments. Writers made the temperature-balance model from a point of view that this temperature rise is coming from the heat rise and the conductivity, and we expressed the temperature rise of DY by using amount of the heat rise and conductivity characteristics of each element. Also, we indicated the method to decide about the selection of the wire size of coils, the section area and deflection sensitivity, with regard to reducing the temperature rise. We confirmed the effect of the temperature rise reduction by about 9 on products, under the condition of 64 kHz horizontal frequency.

In the final stages of VLSI testing, improved quality VLSI testing is an important subject for ensuring reliability in the forwarded VLSI market. On the other hand, developments in high integration technology have resulted in an increased number of functional blocks in VLSI devices and an increased number of gates for each terminal. Consequently, it has become more difficult to improve the quality of VLSI tests. We have developed a new test method in addition to conventional testing methods intended for improving the test coverage in VLSI tests. This new test method analyzes the relationship between IDDq (Quiescent Power Supply Current) of DUT and DUT failure by applying the concept of the toggle rate. Accordingly, in this paper we report that the results of IDDq testing confirm a correlation with defect level.

Some undetectable stuck-at faults called the redundant faults are included in practical combinational circuits. The redundant fault does not affect the functional behavior of the circuit even if it exists. The redundant fault, however, causes undesirable effects to the circuit such as increase of delay time and decrease of testability of the circuit. It is considered that some redundant faults may cause the logical defects in the future. In this paper, firstly, we study the testability of the redundant fault in the combinational circuit by using delay effects. Secondly, we propose a method for generating a test-pair of a redundant fault by using an extended seven-valued calculus, called TGRF (Test-pair Generation for Redundant Fault). TGRF generates a dynamically sensitizable path for the target line which propagates the change in the value on the target line to a primary output. Finally, we show experimental results on the benchmark circuits under the assumptions of the unit delay and the fanout weighted delay models. It shows that test-pairs for some redundant faults are generated theoretically.

An adaptive joint-process IIR filter with generalized lattice structure is constructed. This filter can borrow both FIR and IIR features and simultaneously holds the well-known merits of lattice structure.

An experimental 3 V-only 4 Mb NAND Flash memory with 65 ns access time has been developed using a new charge pump circuit and novel circuit techniques such as folded bit-line architecture. By adopting a new program verify technique, programming time is reduced to 11 µs/Byte.

Ever increasing demand for higher bandwidth memories, which is fueled by multimedia and 3D graphics, seems to be somewhat satisfied with various emerging memory solutions. This paper gives a review of these emerging DRAM architectures and a performance comparison based on a condition to let the readers have some perspectives of the future and optimized graphics systems.

In this paper we present a design method for all-pass networks with consideration of the stability. It is based on the eigen filter method and Remez exchange algorithm is used to obtain the equiripple phase error solution. In the iteration of the proposed algorithm, the eigen values besides maximum eigen value are used in order to obtain a stable all-pass networks.

This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate a test generation procedure previously proposed and reduce the number of test vectors generated, while higher fault coverage is derived. The first technique proposed in this paper, which is applied at the first phase of test generation, is rules of ordering vector pairs to be analyzed, to derive high fault coverage without repeating the analysis for the same vector pairs. The second one is to generate new vector pairs for undetected faults, instead of random vector pairs. Both techniques are based on the idea that faults close to primary inputs should be detected earlier than close to primary outputs. The third technique proposed here is how to construct vector pairs from one input vector in order to accelerate test generation especially for circuits with many primary inputs and scan flip-flops. Experimental results for bench-mark circuits show the effectiveness of the techniques.

A 3.3 V single power-supply 64 Mb flash memory with a DBL programming scheme has been developed and fabricated with 0.4 µm CMOS technology. 50 ns access time and 256 b erase/programming unit-capacity have been achieved by using hierarchical word- and bit-line structures and DBL programming scheme. Furthermore in order to lower operating voltage the HiCR cell is used. The chip size is 19.3 mm13.3 mm.

This paper establishes a relationship among the accepting powers of deterministic, nondeterministic, and alternating one-way auxiliary pushdown automata, for any tape bound below n. Some other related results are also presented.

This paper describes a multimodal dialogue system employing speech input. This system uses three input methods (through a speech recognizer, a mouse, and a keyboard) and two output methods (through a display and using sound). For the speech recognizer, an algorithm is employed for large-vocabulary speaker-independent continuous speech recognition based on the HMM-LR technique. This system is implemented for telephone directory assistance to evaluate the speech recognition algorithm and to investigate the variations in speech structure that users utter to computers. Speech input is used in a multimodal environment. The collecting of dialogue data between computers and users is also carried out. Twenty telephone-number retrieval tasks are used to evaluate this system. In the experiments, all the users are equally trained in using the dialogue system with an interactive guidance system implemented on a workstation. Simplified city maps that indicate subscriber names and addresses are used to reduce the implicit restrictions imposed by written sentences, thus allowing each user to develop his own forms of expression. The task completion rate is 99.0% and approximately 75% of the users say that they prefer this system to using a telephone book. Moreover, there is a significant decrease in nonkeyword usage, i.e., the usage of words other than names and addresses, for users who receive more utterance practice.

We discuss how to determine automatically the number of mixture components in continuous mixture density HMMs (CHMMs). A notable trend has been the use of CHMMs in recent years. One of the major problems with a CHMM is how to determine its structure, that is, how many mixture components and states it has and its optimal topology. The number of mixture components has been determined heuristically so far. To solve this problem, we first investigate the influence of the number of mixture components on model parameters and the output log likelihood value. As a result, in contrast to the mixture number uniformity" which is applied in conventional approaches to determine the number of mixture components, we propose the principle of distribution size uniformity". An algorithm is introduced for automatically determining the number of mixture components. The performance of this algorithm is shown through recognition experiments involving all Japanese phonemes. Two types of experiments are carried out. One assumes that the number of mixture components for each state is the same within a phonetic model but may vary between states belonging to different phonemes. The other assumes that each state has a variable number of mixture components. These two experiments give better results than the conventional method.