A CMOS current-mode companding divider is presented. Currents of both dividend and divisor are compressed into log-domain. Then the logarithm current of divisor is subtracted from the logarithm current of dividend. After expanding the subtraction result, the division function could be achieved. The simulation results indicate that the proposed divider has with good performance at only 1.8 V supply voltage.

In this paper, a high accuracy, high efficiency, and wide current-sensing range current-mode PWM buck converter with on-chip current-sensing technique is presented. The proposed current-sensing circuit uses simple switch technique to achieve high accuracy, high power efficiency, and high line regulation. The test chip is fabricated using TSMC 0.18 µm 1P6M 3.3 V CMOS process. The measurement results show that the buck converter with on-chip current-sensing circuit can operate from 700 kHz to 3 MHz with a supply voltage of 1.5-5 V and the output voltage of 0.5-4.5 V for lithium ion battery applications. The accuracy of the proposed current-sensing circuit is exceeds 89.8% for load current from 50 mA to 500 mA and for temperature from 0C to 100C. The peak power efficiency of the buck converter is up to 95.5%.

A two-quadrant CMOS current-mode plug-in divider using a compact 1/x device is presented. The mismatch errors of 1/x device cancel part of mismatch errors of the proposed divider. The simulation results indicate that the plug-in divider is feasible by the proposed approximation method. The adjustable 1/x device could be applied in difference ranges.

This paper presents a design of an asynchronous peer-to-peer half-duplex/full-duplex-selectable data-transfer system on-chip interconnected. The data-transfer method between channels is based on a 1-phase signaling scheme realized by using multiple-valued current-mode (MVCM) circuits and encoding, which performs high-speed communication. A data transmission is selectable by adding a mode-detection circuit that observes data-transmission modes; full-duplex, half-duplex and standby modes. Especially, since current sources are completely cut off during the standby mode, the power dissipation can be greatly reduced. Moreover, both half-duplex and full-duplex communication can be realized by sharing a common circuit except a signal-level conversion circuit. The proposed interface is implemented using 0.18-µm CMOS, and its performance improvement is discussed in comparison with those of the other ordinary asynchronous methods.

For a globally asynchronous locally synchronous (GALS) system, data transfer mechanisms based on a current-mode multiple valued logic (CMMVL) has been studied to reduce complexity and power dissipation of wires. However, these schemes consume considerable amount of power even in idle states because of the static power caused by their inherent structure. In this paper, new encoder and decoder circuits using CMMVL are suggested to reduce the static power. The effectiveness of the proposed data transfer is validated by comparisons with the previous CMMVL scheme and conventional voltage-mode schemes such as dual-rail and 1-of-4 encodings through simulation with a 0.25-µm CMOS technology. Simulation results demonstrate that the proposed CMMVL scheme significantly reduces power consumption of the previous one and is superior to dual-rail and 1-of-4 schemes over wire length of 2 mm and 4 mm, respectively.

A current-mode squarer/divider circuit with a novel translinear cell is presented for automotive applications. The proposed circuit technique increases the accuracy of the squarer/divider function with better input dynamic range and temperature insensitivity. Simulation results show that the variation of the output current is within ±0.2% over the temperature range from -40 to 140.

This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip transmission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.

This paper presents a high-speed 5454-bit multiplier using fully differential-pair circuits (DPCs) in 0.18 µm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2 V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88 ns with 74.2 mW at 400 MHz from a 1.8 V supply occupying a 0.85 mm2 active area.

A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18 µm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.

The possibility of realizing a CMOS pipelined current-mode A-D converter (ADC) for video applications has been examined. Two times the input current is obtained at the output of a bit-block of a pipelined ADC by subtracting the negative output current from the positive output current in the pseudo-differential configuration. Subtraction of the sub-DAC (D-to-A converter) current from the two times the input current is performed by controlling of the current comparator, which compares the positive and the negative input currents. A prototype chip has been implemented using 0.35 µm CMOS devices. It operates in 28 MS/s, and showed a 42 dB signal-to-noise ratio from the 2 V supply voltage.

This paper presents the design of new fully differential CMOS class A and class AB current-mode transmitters for multi-Gbps serial links. A high multiplexing speed is achieved by multiplexing at low-impedance nodes and inductive shunt peaking with active inductors. The fully complementary operation of the multiplexers and the fully differential configuration of the transmitters minimizes the effect of common-mode disturbances and that of EMI from channels to neighboring devices. Large output current swing is obtained by making use of differential current amplifiers and the differential rail-to-rail configuration. The constant current drawn from the supply voltage minimizes the noise injected into the substrate. The transmitters have been implemented in TSMC's 1.8 V 0.18 µm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V device models. Simulation results confirm that the proposed transmitters are capable of transmitting data at 10 Gbps.

A tunneling magnetoresistive(TMR)-based logic-in- memory circuit, where storage functions are distributed over a logic-circuit plane, is proposed for a low-power VLSI system. Since the TMR device is regarded as a variable resistor with a non-volatile storage capability, any logic functions with external inputs and stored inputs can be performed by using the TMR-based resistor/transistor network. The combination of dynamic current-mode circuitry and a TMR-based logic network makes it possible to perform any switching operations without steady current, which results in power saving. A design example of an SAD unit for MPEG encoding is discussed, and its advantages are demonstrated.

A simple high-speed low input impedance CMOS current comparator is presented. The circuit uses improved Wilson current-mirror to perform subtraction. Negative feedback is employed to reduce the input impedance of the circuit. HSPICE is used to verify the circuit performance with standard 0.5 µm CMOS technology. Simulation results demonstrate propagation delay of 1.02 ns, average power consumption of 0.9 mW, and input impedance of 137 Ω for 0.1 µA input current at the supply voltage of 3 V.

This paper presents three new circuits for the realisation of grounded inductors of lossy and lossless types. The active element used is the recently proposed current differencing buffered amplifier which is proven to be useful for the realisation of different current mode circuits. Applications of the proposed circuits are shown. Simulation results are included to verify theory.

Conventional delay-insensitive (DI) data encodings require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, a DI data transfer mechanism based on current-mode multiple valued logic (CMMVL), where N-bit data transfer can be performed with only N+1 wires, is proposed. The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25-µm CMOS technology. Simulation results with wire lengths of 4 mm or larger demonstrate that the CMMVL scheme significantly reduces delay-power product values of the dual-rail encoding with data rate of 5 MHz or more and the 1-of-4 encoding with data rate of 18 MHz or more.

Based on the similarity in current-voltage characteristics of resonant-tunneling diodes (RTDs) and tunneling-type superconductive Josephson junctions, novel current-mode logic circuits consisting of four RTDs have been proposed. NAND and NOR functions, as well as AND and OR, can be obtained in a simple circuit configuration. SPICE simulation showed that the present circuits can operate at a clock frequency as high as 200 GHz.

In this paper, we propose the use of second-order slope compensation for a current-mode PWM buck converter. First, the current feedback loop in a current-mode PWM buck converter using a conventional slope compensation is analyzed by the small-signal transfer function. It becomes clear that the stability and frequency bandwidth of the current feedback loop is affected by the external input voltage and the output voltage of the converter. Next, the loop with second-order slope compensation is analyzed, and the result shows that the loop becomes unconditionally stable with the adoption of second-order slope compensation with appropriate parameter values and a current sensing circuit whose current is sensed across an impedance that is inversely proportional to the input voltage. In order to verify our theory, we designed whole circuits of a current-mode PWM buck converter including the new inductor current sensing circuit and the second-order voltage generator circuit using device parameters from the 0.6 µm CMOS process. The circuit simulation results under the conditions of 4 MHz switching frequency, 3.6 V input voltage and 2.4 V output voltage are presented.

Linear transformation transistor-only high-order current-mode filters are presented in this Letter. Based on the systematic design procedure, we can realize high-order current-mode filters employing switched-current technique efficiently. Only two kinds of switched-current basic cells are needed in our design to obtain simple architectures. The fifth-order Chebychev lowpass filter is designed to verify the proposed synthesis method. Simulation results that confirm the theoretical analysis are obtained.

A new current-mode quadrature oscillator circuit using two differential voltage current conveyors (DVCCs), two grounded capacitors and two grounded resistors is presented. Two high output impedance sinusoid current sources with 90phase difference are available in the proposed circuit. The oscillation condition and oscillation frequency are orthogonally controllable. The use of only grounded capacitors and resistors makes the proposed circuit ideal for integrated circuit implementation. Simulation results are also included.

A second-generation CMOS current conveyor (CCII) consisting of a rail-to-rail complementary N- and P-channel differential input stage for the voltage input, a class AB push-pull stage for the current input, and current mirrors for the current outputs is developed. The CCII was implemented using a double-poly triple-metal 0.6 µm n-well CMOS process, to confirm its operation experimentally. A prototype chip achieves a rail-to-rail swing 2.4 V under 2.5 V power supplies and shows the exact voltage and current following performances up to 100 MHz. These performances make the CCII proposed herein quite useful for a building block of current-mode circuits. The prototype CCII is applied to current-mode filters to demonstrate the wideband signal processing capabilities.