A parallel current-mode multilevel identifying circuit for flash memories is proposed. The sensing scheme based on the CMOS cross-coupled structure modified from the clamped bit-line sense amplifier achieves high speed and low power dissipation. The offset of the proposed sense amplifier due to mismatch is also reduced significantly. The circuit has been fabricated using 0.6 µm CMOS technology. The simulation and measurement indicate the sensing speed reaches 1 ns at 3 V supply voltage with average power consumption about 2 mW at 50 MHz.

A CMOS current-mode continuous-time band-pass filter using the positive feedback Q (quality factor) - enhancement technique is presented in this paper. Q of the proposed filter can be mainly determined by the ratio of the two MOSFETs' transconductances in a Q-setting part, not by the ratio of two capacitance values similar to most of conventional band-pass filters. This filter can realize high Q value in spite of small chip area. Therefore, when higher value of Q is needed, the proposed filter does not need large capacitor which occupies large area on an IC chip. The proposed filter spends smaller chip area than the conventional one under the condition of Q>2. The proposed circuit is simulated by Spectre to confirm its characteristics.

This paper describes a low-power-supply 2-GHz CMOS up-converter. A current-mode mixing method using current adding and self-switching mixers is proposed for 1-V operation. The current-mode up-converter achieves conversion gain of 6.7 dB and linearity of 6.5-dBm OIP3 at 1 V. Balanced configuration and DC offset canceller reduce LO leakage below -40 dBc even with 20-mV Vth mismatches. The bias circuit of the IC is designed to maintain constant conversion gain for variation of temperature for practical usage. The measurement results indicate the proposed up-converter is applicable for future wireless systems.

This paper investigates multiple-valued code-division multiple access (MV-CDMA) techniques and circuits for intra/inter-chip communication to achieve efficient data transmission in VLSI systems. To address the problems caused by interconnection complexity, we transmit multiplexed signals inside LSI systems employing pseudo-random orthogonal m-sequences as information carriers. A new class of multiple-valued CDMA techniques for intra-chip communication is discussed to demonstrate the feasibility of eliminating co-channel interference caused by a propagation delay of signals, e.g., clock skew. This paper describes the circuit configuration and performance evaluation of MV-CDMA systems for intra-chip communication. We first explain the principle of MV-CDMA technique, and then propose a bidirectional current-mode CMOS technique to realize compact correlation circuits for CDMA. Finally, we show the Spice and MATLAB simulation results of MV-CDMA systems, which indicate the excellent capabilities of eliminating co-channel interference.

In this paper, we propose a universal biquad filter that can realize all types of 2nd-order functions, such as Low-pass Filters (LPF), High-Pass Filters (HPF), Band-Pass Filters (BPF), Band-Elimination Filters (BEF), and All-Pass Filters (APF). Also, the filter types can be programmable digitally with built-in switches. The proposed circuit can be realized by using a CMOS technology that is suitable for a mixed digital-analog LSI. In addition, the circuit can operate in high frequencies with a low power supply voltage because it is based on a current-mode circuit. Finally, the proposed circuit is simulated by PSpice to confirm its characteristics.

This paper introduces current-mode biquad using multiple current output operational transconductance amplifiers (OTAs) and grounded capacitors. The circuit configuration is obtained from a second-order integrator loop structure with loss-less and lossy integrators. The proposed circuit can realize low-pass, band-pass, high-pass, band-stop and all-pass transfer functions by suitably choosing the input and output terminals. And the circuit characteristics can be electronically tuned through adjusting the transconductance gains of OTAs. It is also made clear that the proposed circuit has very low sensitivities with respect to the circuit active and passive elements. An example is given together with simulated results by PSpice.

In this paper, a new design idea for class A CMOS second generation current conveyor (CCII) is discussed. Based on the proposed idea, a new architecture for a CMOS CCII is presented. The proposed circuit is free from body effect and provides high performance in terms of input resistance and transfer gain errors. HSPICE simulation results also have shown remarkable performance over the wide bandwidth.

A current-mode folding and interpolating analog to digital converter (ADC) architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 µm n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity (DNL) of 0.5LSB, an integral nonlinearity (INL) of 1.0LSB, 20 Ms/s of the data conversion rate, and the power dissipation of 180 mW with a power supply of 5 V.

This paper reviews analog-circuit researches in the 1990's especially from an academic-side point of view with the aim of pursuing what becomes important in the 21st century. To achieve this aim a large number of articles are surveyed and more than 200 are listed in References.

A new current-mode (CM) multifunction filter with single input and three outputs (SITO) employing only three dual output current conveyors (DO-CCII) and four passive elements is presented. The proposed filter realizes three basic filter functions simultaneously all at high impedance outputs. No component matching is required and all the passive and active sensitivities are low.

This paper describes how to generate, analyze and design a novel current-mode filter model using tunable multiple-output operational transconductance amplifiers and grounded capacitors (MO-OTA-Cs) for synthesizing both transmission poles and zeros. Transfer functions of low-order, high-order, general type, and special type are realized based on the filter model. The theory focuses mainly on establishing a relationship between the cascaded MO-OTA-Cs and the multiple-loop feedback matrix, which makes the structural generation and design formulas. Adopting the theory allows us to systematically generate many interesting new configurations along with some known structures. All the filter architectures contain only grounded capacitors, which can absorb parasitic capacitances and require smaller chip areas than floating ones. The paper also presents numerical design examples and simulation results to confirm the theoretical analysis.

This paper proposes a realization of power factor function generator having an arbitrary base and power factor which are determined by the ratios of the currents provided from outside of the circuit. The circuit characteristics do not depend on any transistor parameters, temperature, and other environmental conditions. The circuit operation is based on current mode that has a capability of low power supply voltage operation below than 2.0 V. SPICE simulation has been carried out using 0.7 µm BiCMOS parameters and shows quite good transfer characteristics.

This paper describes an IC implementation of current-mode chaotic neuron circuit for the chaotic neural network. The chaotic neuron circuit which composes of a first generation switched-current integrator and a conventional current amplifier is fabricated in a standard 0.8 µ m CMOS technology. Experimental results of the chaotic neuron circuit reproduce the dynamical behavior of the chaotic neuron model.

A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by VT (threshold voltage), compared with the conventional double cascode current mirror. The νMOS threshold detector is built on a νMOS current comparator originally composed of νMOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the transfer region can be increased 6.3-fold compared with that in the conventional comparator. Along with improved operation of the novel current comparator, the discriminative ability of the proposed νMOS threshold detector is also increased. The performances of the proposed circuits are validated by HSPICE with Motorola 1.5 µm CMOS device parameters. Furthermore, the operation of a νMOS current mirror is also confirmed through experiments on test chips fabricated by VDEC*. The active area of the proposed νMOS current mirror is 63 µm 51 µm.

This paper describes a 10 bit CMOS current-mode A/D converter with a current predictor and a modular current reference circuit. A current predictor and a modular current reference circuit are employed to reduce the number of comparator and reference current mirrors and consequently to decrease a power dissipation. The 10 bit current-mode A/D converter is fabricated by the 0.6 µm n-well double poly/triple metal CMOS technology. The measurement results show the input current range of 16 µA to 528 µA, DNL and INL of 0.5 LSB and 1.0 LSB, conversion rate of 10 Msamples, and power dissipation of 94.4 mW with a power supply of 5 V. The effective chip area excluding the pads is 1.8 mm 2.4 mm.

In this paper, current-mode integrators which consist of only n-channel depletion-mode FET and their application to filters are presented. Lossy integrator is simply realized with a capacitor and a grounded gate FET. Lossless integrator can be obtained by providing a lossy integrator with a positive feedback. To do this, multi-output current mirror is proposed. To reduce 2nd-order harmonic and THD of the filter, unbalanced/balanced conversion circuit is proposed. As an application example, 3rd-order leapfrog low-pass Chebyshev filter is simulated with GaAs MESFET process parameters. Simulation results show good performances.

The required building blocks of CMOS fuzzy chips capable of performing as adaptive fuzzy systems are described in this paper. The building blocks are designed with mixed-signal current-mode cells that contain low-resolution A/D and D/A converters based on current mirrors. These cells provide the chip with an analog-digital programming interface. They also perform as computing elements of the fuzzy inference engine that calculate the output signal in either analog or digital formats, thus easing communication of the chip with digital processing environments and analog actuators. Experimental results of a 9-rule prototype integrated in a 2. 4-µm CMOS process are included. It has a digital interface to program the antecedents and consequents and a mixed-signal output interface. The proposed design approach enables the CMOS realization of low-cost and high-inference fuzzy systems able to cope with complex processes through adaptation. This is illustrated with simulated results of an application to the on-line identification of a nonlinear dynamical plant.

The second-generation CMOS current conveyors are developed for high-frequency analog signal processing. It consists of a source follower for the voltage input and a regulated current mirror for the current input and output. The voltage and current input stages are also coupled by a current mirror to reduce the impedance of the current input port. Simulations show that this architecture provides the high input/output conductance ratio and the inherent voltage and current transfer bandwidths extending beyond 100 MHz. The prototype chips fabricated using 0. 6 µm CMOS process have confirmed the simulated performances, though the voltage and current bandwidth are limited to 20 MHz and 35 MHz, respectively, by the built-in capacitances of the bonding pads.

In this letter, a realization of current-mode active filter using current followers as active element is described. We show the constructions of second-order lowpass, highpass and bandpass filters. The high-order filters can be realized by a cascade connection of these second filters. As examples, the second-order lowpass and highpass filters are designed for frequency of 5 MHz. The effectiveness of the proposed method is demonstrated through SPICE simulation.

An 8 bit current-mode folding and interpolation analog to digital converter (ADC) with three-level folding amplifiers is proposed in this paper. A current-mode three-level folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0. 8 µ m n-well CMOS double metal/single poly process occupies the chip area of 2. 2 mm 1. 6 mm. The experimental result shows the power dissipation of 33. 6 mW with a power supply of 5 V.