A stored channel simulator for digital mobile radio enviroments is proposed, which enables the field tests in the laboratory under identical conditions, since it can reproduce the actual multipath radio channels by using the channel impulse responses (CIR's) measured in the field. Linear interpolation of CIR is introduced to simplify the structure of the proposed simulator. The performance of the proposed simulator is confirmed by the laboratory tests.

In practical applications of digital filters it is more realistic to treat multiplier coefficients as finite intervals than restricting them to infinite or very long word-length representations. However, this can not be done it the frequency response performance under interval assumption is difficult to analyze. In this paper, it is proved that stable lattice allpass filters possess bounded continuous phase response when lattice parameters vary in bounded intervals. It is shown that sharp bounds on the interval phase response can be computed easily at an arbitrary frequency using a simple recursive procedure. Application of this property to the problem of finite word-length lattice allpass filter design is also discussed. By formulating this problem as an interval design it is possible to solve it efficiently independent of the number system used to represent multiplier coefficients.

This paper describes the performance of AlGaAs/GaAs HBT's developed for power applications. Their applicability to power amplifiers used in digital mobile radio communications is examined through measurement and numerical simulation, considering both power capability and linearity. Power HBT's with carbon-doped base layers showed DC current gains over 90. A linear gain of 19.2 dB, a maximum output RF power of 32.5 dBm, and a power added efficiency of 56 percent were obtained at 950 MHz. Numerical simulations showed that the power efficiency of HBT amplifiers could be improved by using harmonic trap circuits. Intermodulation measurements showed that third-order distortions were at most 21 dBc level at the 1-dB gain compression point. RF spectrum simulations using π/4 shift QPSK modulation showed that side-band spectrum generation was less than 45 dBc level at points 50 kHz off of the carrier frequency. These properties indicate that the power handling capabilities and linearity of HBT amplifiers offer promising potentials for digital mobile radio communications.

Most of actual environmental systems show a complicated fluctuation pattern of non-Gaussian type, owing to various kinds of factors. In the actual measurement, the fluctuation of random signal is usually contaminated by an external noise. Furthermore, it is very often that the reliable observation value can be obtained only within a definite fluctuating amplitude domain, because many of measuring equipments have their proper dynamic range and original random wave form is unreliable at the end of amplitude fluctuation. It becomes very important to establish a new signal detection method applicable to such an actual situation. This paper newly describes a dynamical state estimation algorithm for a successive observation contaminated by the external noise of an arbitrary distribution type, when the observation value is measured through a finite dynamic range of measurement. On the basis of the Bayes' theorem, this method is derived in the form of a wide sense digital filter, which is applicable to the non-Gaussian properties of the fluctuations, the actual observation in a finite amplitude domain and the existence of external noise. Differing from the well-known Kalman's filter and its improvement, the proposed state estimation method is newly derived especially by paying our attention to the statistical information on the observation value behind the saturation function instead of that on the resultant noisy observation. Finally, the proposed method is experimentally confirmed too by applying it to the actual problem for a reverberation time measurement from saturated noisy observations in room acoustics.

This paper proposes a technique for estimating speech parameters in noisy environment. The technique uses a spectral model represented by generalized cepstrum and estimates the generalized cepstral coefficients from the speech which has been degraded by additive background noise. Parameter estimation is based on maximum a posteriori (MAP) estimation procedure. An iterative approach which has been formulated for all-pole modeling is applied to the generalized cepstral modeling. Generalized cepstral coefficients are obtained by an iterative procedure that consists of the unbiased estimation of log spectrum and noncausal Wiener filtering. Since the generalized cepstral model includes the all-pole model as a special case, the technique can be viewed as a generalization of the all-pole modeling based on MAP estimation. The proposed technique is applied to the enhancement of speech and several experimental results are also shown.

In multidimensional signal sampling, the orthogonal sampling scheme is the simplest one and is employed in various applications, while a non-orthogonal sampling scheme is its alternative candidate. The latter sampling scheme is used mainly in application where the reduction of the sampling rate is important. In three-dimensional (3-D) signal processing, there are two typical sampling schemes which belong to the non-orthogonal samplings; one is face-centered cubic sampling (FCCS) and the other is body-centered cubic sampling (BCCS). This paper proposes a new design method for 3-D band-limiting FIR filters required for such non-orthogonal sampling schemes. The proposed method employs the McClellan transformation technique. Unlike the usual 3-D McClellan transformation, however, the proposed design method uses 2-D prototype filters and 2-D transformation filters to obtain 3-D FIR filters. First, 3-D general sampling theory is discussed and the two types of typical non-orthogonal sampling schemes, FCCS and BCCS, are explained. Then, the proposed design method of 3-D bandlimiting filters for these sampling schemes is explained and an effective implementation of the designed filters is discussed briefly. Finally, design examples are given and the proposed method is compared with other method to show the effectiveness of our methos.

It is known that the resolution conversion based on orthogonal transform has a problem that is difference of luminance between the converted image and the original. In this paper, the scale factor of the system employing various orthogonal transforms is generally formulated by considering the DC gain, and the condition of alias free for DC component is indicated. If the condition is satisfied, then the scale factor is determined by only the basis functions.

We have developed a digital coprocessor with a dynamically reconfigurable pipeline architecture specified for a layered neural network which executes on-chip learning. The coprocessor attains a learning speed of 18 MCUPS that is approximately twenty times that of the conventional DSP. This coprocessor obtains expansibility in the calculation through a larger multi-layer, network by means of a network decomposition and a distributed processing approach.

To realize next-generation high performance ULSI processors, it is a very important issue to reduce the critical delay path which is determined by a cascade chain of basic gates. To design highly parallel digital operation circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the non-linear digital system. On the other hand, the use of the linear concept in the digital system seems to be very attractive because analytical methods can be utilized. To meet the requirement, we propose a new design method of highly parallel linear digital circuits for unary operations using the concept of a cycle and a tree. In the linear digital circuit design, the analytical method can be developed using a representation matrix, so that the search procedure for optimal locally computable circuits becomes very simple. The evaluations demonstrate the usefulness of the circuit design algorithm.

The advantages of a neuro-chip architecture based on a DRAM are demonstrated through a discussion of the general issuse regarding a memory based neuro-chip architecture and a comparison with a chip based on an SRAM. The performance of both chips is compared assuming digital operation, a 1.5-V supply voltage, a 106-synapse neural network capability, and a 0.5-µm CMOS design rule. The use of a one-transistor DRAM cell array for the storage of synapse weights results in a chip 55% smaller than an SRAM based chip with the same 8-Mbit memory capacity and the same number of processing elements. No additional operations for refreshing the DRAM cell array are necessary during the processing of the neural networks. This is because all the synapse weights in the array are transferred to the processing elements during the processing and the DRAM cells in the array are automatically refreshed when they are selected. The precharge operation of the DRAM cell array degrades the processing speed, however a processing speed of 1.37 GCPS is expected for the DRAM based chip. That speed is comparable to the 1.71 GCPS for the SRAM based chip with the same 256 parallel-processing elements. A DRAM cell array has the additional advantage of lower power dissipation in this specific usage for the neuro-chip. The dynamic operation of the DRAM cell array results in a 10% lower operating power dissipation than a chip using an SRAM cell array at the same processing speed of 1.37 GCPS. That lower operating power dissipation enables a DRAM based chip to run on a 1.5-V dry cell for longer under intermittent daily use even though the SRAM cell array has little power dissipation in data-holding mode.

This review presents research topics and results on digital signal processing in the last twenty years in Japan. The main parts of the review consist of design and analysis of multidimensional digital filters, multiple-valued logic circuits and number systems for signal processing, and general purpose signal processors.

Oversampled analog-to-digital (A/D) converters based on sigma-delta (ΣΔ) modulation are attractive for VLSI implementation because they are especially tolertant of circuit nonidealities and component mismatch. Oversampled ΣΔ modulator has some points which must be improved. Some of these problems are based on the small input signal and the integrator leak. In this paper,ΣΔ A/D converter having a dither circuit to improve the linearity and the compensation technique of the integer leak are presented. By the simulation, the most suitable dither to improve the linearity of the modulator is obtained as follows: the amplitude is 1/150 of input signal maximum amplitude, the frequency is 4-times of the signal-band. Using the compensation circuit of the integrator leak, 72 dB of dynamic range is obtained when op-amp gain is 30 dB.

This paper briefly considers future broadcasting technologies, including digital television as a system for the near future and three-dimensional television as a part of a system to be developed rather later. However, due to limitations of space, this paper discusses only video technologies in detail. First, the status of bit reduction technologies for digital television is described and then satellite digital broadcasting and terrestrial digital broadcasting are also discussed. The authors stress the necessity of the further development of digital video compression technologies. Later, we discuss three-dimensional television, we describe requirements for the service and the present status of the technologies. And last, the paper considers the future prospects for a three-dimensional television service.

The approximation of the gain characteristics of linear phase FIR digital filters is reduced to the approximation by cosine polynomials. Therefore we can easily obtain an optimum solution under the LMS of Chebyshev error criterion. However the optimum solution does not always meet practical specifications, especially in the case where the gain is specified strictly at some angular frequencies. On the other hand in such a case, it is known that interpolation technique can be suitably applied for the approximation mentioned above. However, in this case, we encounter another difficulty in the approximation caused by interpolation. In order to overcome the above difficulty, this paper proposes a new method utilizing both of the interpolation and LMS techniques. Some parameters included in approximating functions are used to satisfy prescribed interpolating conditions and the other parameters are used to minimize the approximation error under the LMS criterion. In addition, interpolation technique is extended to include the case in which also higher derivatives are taken into interpolation conditions to make smooth interpolation. An example is shown to illustrate the effectiveness of the proposed method.

This paper proposes a suitable combination of the digital modulation schemes and the coding-rate of forward error correction (FEC) schemes for satellite digital video communication networks. The comparative study is carried out by computer simulation considering non-linearly amplified, narrow bandwidth satellite channels with adjacent channel interference signals. The proposed system employs an offset QPSK modulation scheme supported by the coding-rate of 7/8 convolutional encoding and Viterbi decoding to realize high-quality and compact spectrum characteristics in non-linear channels. By employing a 32Mbps DPCM video codec, the developed prototype system achieves a post demodulated S/N ratio of higher than 52dB. Moreover, it achieves high protection ratio against co-channel interference than conventional analog FM systems. The optimized digital video transmission system makes it possible to transmit high-quality NTSC video signals over non-linearly amplified narrow bandwidth satellite channels, for example 27MHz or 36MHz bandwidth transponders, with high-security digital encryption.

In this paper, we discuss secure protocols for shared computation of algorithms associated with digital signature schemes based on discrete logarithms. Generic solutions to the problem of cooperatively computing arbitraty functions, though formally provable according to strict security notions, are inefficient in terms of communication--bits and rounds of interaction--; practical protocols for shared computation of particular functions, on the other hand, are often shown secure according to weaker notions of security. We propose efficient secure protocols to share the generation of keys and signatures in the digital signature schemes introduced by Schnorr (1989) and ElGamal (1985). The protocols are built on a protocol for non-interactive verifiable secret sharing (Feldman, 1987) and a novel construction for non-interactively multiplying secretly shared values. Together with the non-interactive protocols for shared generation of RSA signatures introduced by Desmedt and Frankel (1991), the results presented here show that practical signature schemes can be efficiently shared.

The authors recently proposed a design method of stable IIR digital filters based on the interpolation by rational characteristic functions of filters, for a set of values of these characteristic function and, in addition, their higher derivatives prescribed at a number of frequency. This method can be further extended so that, despite usage of a less number of interpolation points, almost the same filter characteristics as one obtained by the former method can be realized. This paper presents an improved design method for making the transfer function meet strict magnitude specifications. The method proposed in this paper is especially efficient for designing a filter whose characteristics is specified not only in the passband but also in the transition band with relatively narrow bandwidth.

This paper studies a method for a parallel implementation of digital half toning technique, which converts continuous tone images into monotone one without losing fidelity of images. A new modified algorithm for half toning is proposed, which is able to be implemented on a rectangular or one dimensional parallel multi-processor array as a part of extensions of space partitioning image processings. The purpose of this paper is primarily to apply space partitioning local image processing technique to nonlinear recursive algorithms. The target is to achieve a fast half toning with high quality. For that propose, local directional error diffusion techniques will be introduced, which enable original recursive error diffusion half toning to be converted into a local processing algorithm without losing its original advantages of producing high quality images. The characteristics of proposed methods will be analyzed and the advantages of our algorithm of high speed processing and high quality will be demonstrated by showing the results of simulations for typical examples.

This paper deals with the theory and design method of an efficient radix-4 divider using carry-propagation-free adders based on redundant binary {-1,0,+1} representation. The usual method of normalizing the divisor in the range [1/2,1) eliminates the advantages of using a higher radix than two, bacause many digits of the partial remainder are required to select the quotient digits. In the radix-4 case, it is shown that it is possible to select the quotient digits to refer to only the four (in the usual normalizing method it is seven) most significant digits of the partial remainder, by scaling the divisor in the range [12/8,13/8). This leads to radix-4 dividers more effective than radix-2 ones. We use the hyperstring graph representation proposed in Ref.(18) for redundant binary adders.

We propose a design method for a two-channel perfect reconstruction FIR filter banks employing linear-phase filters. This type of filter bank is especially important in splitting image signals into frequency bands for subband image cording. Because in such an application, it is necessary to use the combination of linear-phase filters and symmetric image signal, namely linear phase signal to avoid the increase in image size caused by filtering. In this paper, first we summarize the design conditions for two-channel filter banks. Next, we show that the design problem is reduced to a very simple linear equation, by using a half-band filter as a lowpass filter. Also the proposed method is available to lead filters with fewer complexity, which enable us to use simple arithmetic operations. For subband coding, the property is important because it reduces hardware complexity.