Locally repairable codes, which can repair erased symbols from other symbols, have attracted a good deal of attention in recent years because its local repair property is effective on distributed storage systems. (ru, δu)u∈[s]-locally repairable codes with multiple localities, which are an extension of ordinary locally repairable codes, can repair δu-1 erased symbols simultaneously from a set consisting of at most ru symbols. An upper bound on the minimum distance of these codes and a construction method of optimal codes, attaining this bound with equality, were given by Chen, Hao, and Xia. In this paper, we discuss the parameter restrictions of the existing construction, and we propose explicit constructions of optimal codes with multiple localities with relaxed restrictions based on the encoding polynomial introduced by Tamo and Barg. The proposed construction can design a code whose minimum distance is unrealizable by the existing construction.

This paper analyzes the time domain Reed Solomon Decoder with FPGA implementation. Data throughput and area is carefully evaluated compared with typical frequency domain Reed Solomon Decoder. In this analysis, three hardware architecture to enhance the data throughput, namely, the pipelined architecture, the parallel architecture, and the truncated arrays, is evaluated, too. The evaluation reveals that the number of the consumed resources of RS(255, 239) is about 20% smaller than those of the frequency domain decoder although data throughput is less than 10% of the frequency domain decoder. The number of the consumed resources of the pipelined architecture is 28% smaller than that of the parallel architecture when data throughput is same. It is because the pipeline architecture requires less extra logics than the parallel architecture. To get higher data throughput, the pipelined architecture is better than the parallel architecture from the viewpoint of consumed resources.

In conventional spread spectrum (SS) watermarking schemes, random sequences are used for the modulation of watermark information. However, because of the mutual interference among those sequences, it requires complicated removal operation to improve the performance. In this paper, we propose an efficient spread spectrum watermarking scheme by introducing the orthogonal frequency divisiion multiplexing (OFDM) technique at the modulation of watermark information. The SS sequences in the proposed method are the DCT basic vectors modulated by a pseudo-random number (PN) sequence. We investigate the SS-based method considering the host interference at the blind detection scenario and analyze the noise caused by attacks. Because every operation is invertible, the quantization index modulation (QIM)-based method is applicable for the OFDM modulated signals. We also consider the property of watermark extracting operation in SS-based and QIM-based method and formalize their models of noisy channel in order to employ an error correcting code. The performance of their methods with error correcting code is numerically evaluated under the constraints of same distortion level in watermarked content. The experimental results indicated a criteria for the selection of SS-based and QIM-based methods for given content, which is determined by the amount of host interference. In case that the host interference is 0.8 times smaller than a watermark signal, the SS-based method is suitable. When it is 1.0 times larger, the QIM-based method should be selected.

A comprehensive model is presented for estimating the bit error rate (BER) of write disturbance in a resistive memory composed of a cross-point array. While writing a datum into the selected address, the non-selected addresses are biased by word-line (WL) and bit-line (BL). The stored datum in the non-selected addresses will be disturbed if the bias is large enough. It is necessary for the current flowing through the non-selected address to be calculated in order to estimate the BER of the write disturbance. Since it takes a long time to calculate the current flowing in a large-scale cross-point array, several simplified circuits have been utilized to decrease the calculating time. However, these simplified circuits are available to the selected address, not to the non-selected one. In this paper, new simplified circuits are proposed for calculating the current flowing through the non-selected address. The proposed and the conventional simplified circuits are used, and on that basis the trade-off between the write disturbance and the write error is discussed. Furthermore, the error correcting code (ECC) is introduced to improve the trade-off and to provide the low-cost memory chip matching current production lines.

Rapid process scaling and the introduction of the multilevel cell (MLC) concept have lowered costs of NAND Flash memories, but also degraded reliability. For this reason, the memories are depending on strong error correcting codes (ECCs), and this has enabled the memories to be used in wide range of storage applications, including solid-state drives (SSDs). Meanwhile, too strong error correcting capability requires excessive decoding complexity and check bits. In NAND Flash memories, cell errors to neighborhood voltage levels are more probable than those to distant levels. Several ECCs reflecting this characteristics, including limited-magnitude ECCs which correct only errors with a certain limited magnitude and low-density parity check (LDPC) codes, have been proposed. However, as most of these ECCs need the multiple bits in a cell for encoding, they cannot be used with multipage programing, a high speed programming method currently employed in the memories. Also, binary ECCs with Gray codes are no longer optimal when multilevel voltage shifts (MVSs) occur. In this paper, an error correction method reflecting the error characteristic is presented. This method detects errors by a binary ECC as a conventional manner, but a nonbinary value or whole the bits in a cell, are subjected to error correction, so as to be corrected into the most probable neighborhood value. The amount of bit error rate (BER) improvement is depending on the probability of the each error magnitude. In case of 2bit/cell, if only errors of magnitude 1 and 2 can occur and the latter occupies 5% of cell errors, acceptable BER is improved by 4%. This is corresponding to extending 2.4% of endurance. This method needs about 15% longer average latency, 19% longer maximum latency, and 15% lower throughput. However, with using the conventional method until the memories' lifetime number of program/erase cycling, and the proposed method after that, BER improvement can be utilized for extending endurance without latency and throughput degradation until the switch of the methods.

Storage-Class Memory (SCM) and NAND flash hybrid Solid-State Drive (SSD) has advantages of high performance and low power consumption compared with NAND flash only SSD. In this paper, first, three SSD configurations are investigated. Three different SCMs are used with 0.1 µs, 1 µs and 10 µs read/write latencies, respectively, and the required SCM/NAND flash capacity ratios are analyzed to maintain the same SSD performance. Next, by using the three SSD configurations, the variation of SSD reliability, performance and cost are analyzed by changing error correction strengths. The SSD reliability of acceptable SCM and NAND flash Bit Error Rates (BERs) is limited by achieving specified SSD performance with error correction, and/or limited by SCM and NAND flash parity size and SSD cost. Lastly, the SSD replacement cost is also analyzed by considering the limitation of NAND flash write/erase cycles. The purpose of this paper is to provide a design guideline for obtaining high performance, highly reliable and cost-effective SCM/NAND hybrid structure SSD with ECC.

As semiconductor devices scale into deep sub-micron regime, the reliability issue due to radiation-induced soft errors increases in on-chip memory systems. Neutron-induced soft errors transiently upset adjacent information of multiple cells in these systems. Although single error correction and double error detection (SEC--DED) codes have been employed to protect on-chip memories from soft errors, they are not sufficient against multiple cell upsets (MCUs). SEC--DED and double adjacent error correction (SEC--DED--DAEC) codes have recently been proposed to address this problem. However, these codes do not the resolve mis-correction of double non-adjacent errors because syndromes for double non-adjacent errors are equal to that of double adjacent errors. The occurrence of this mis-correction in region of critical memory section such as operating systems may lead to system malfunction. To eliminate mis-correction, the syndrome spaces for double adjacent and double non-adjacent errors are not shared using the matrix with reversed colexicographic order. The proposed codes are implemented using hardware description language and synthesized using 32 nm technology library. The results show that there is no mis-correction in the proposed codes. In addition, the performance enhancement of the decoder is approximately 51.9% compared to double error correction codes for on-chip memories. The proposed SEC--DED--DAEC codes is suitable for protecting on-chip memory applications from MCUs-type soft errors.

The amplitude damping (AD) quantum channel is one of the models describing evolution of quantum states. The construction of quantum error correcting codes for the AD channel based on classical codes has been presented, and Shor et al. proposed a class of classical codes over F3 which are efficiently applicable to this construction. In this study, we expand Shor's construction to that over F7, and succeeded to construct an AD code that has better parameters than AD codes constructed by Shor et al.

Let PA(n, d) be a permutation array (PA) of order n and the minimum distance d. We propose a new construction of the permutation array PA(pm, pm-1k) for a given prime number p, a positive integer k < p and a positive integer m. The resulted array has (|PA(p,k)|p(m-1)(p-k))m rows. Compared to the other constructions, the new construction gives a permutation array of far bigger size with a large minimum distance, for example, when k ≥ 2p/3. Moreover the proposed construction provides an algorithm to find the i-th row of PA (pm, pm-1k) for a given index i very simply.

Soft error has become an increasingly significant concern in modern micro-processor design, it is reported that the instruction-level temporal redundancy in out-of-order cores suffers an performance degradation up to 45%. In this work, we propose a fault tolerant architecture with fast error correcting codes (such as the two-dimensional code) based on double execution. Experimental results show that our scheme can gain back IPC loss between 9.1% and 10.2%, with an average around 9.2% compared with the conventional double execution architecture.

In reliable multicast, feedback and recovery traffic limit the performance and scalability of the multicast session. In this paper, we present an improvement to the many-to-many reliable multicast protocol, Group-Aided Multicast protocol (GAM), with a local-group based recovery by making use of forward error correction (FEC) locally in addition to NACK/retransmission. In contrast to the original GAM, which only makes use of NACK-based recovery, our scheme produces FEC packets and multicasts the packets within the scope of a local group in order to correct uncorrelated errors of the local members in each group of the multicast session, which reduces the need for NACK/retransmission. By using our scheme, redundancy traffic can be localized in each group within a multicast session, and the overall recovery traffic can be reduced.

For reducing bit errors on wireless channels, we have proposed the multiroute coding scheme on multiple routes for wireless multihop networks. In this paper, we introduce ARQ to our multiroute coding scheme. In our multiroute coding scheme, a destination node combines and decodes subpackets which are encoded and divided by a source node. Each intermediate node relays a subpacket, that is, only a part of a packet. Therefore, intermediate nodes cannot detect packet errors, and only a destination node can do so after combining and decoding subpackets. We propose an ARQ scheme between a source node and a destination node. We analyze the proposed ARQ scheme and evaluate the system performance.

We have researched high dimensional parity-check (HDPC) codes that give good performance over a channel that has a very high error rate. HDPC code has a little coding overhead because of its simple structure. It has hard-in, maximum detected bit flipping (MDBF) decoding that has reasonable decoding performance and computational cost. In this paper, we propose a modified algorithm for MDBF decoding and compare the proposed MDBF decoding with conventional hard-in decoding.

Solving the error correcting code is an important goal with regard to communication theory. To reveal the error correcting code characteristics, several researchers have applied a statistical-mechanical approach to this problem. In our research, we have treated the error correcting code as a Bayes inference framework. Carrying out the inference in practice, we have applied the NMF (naive mean field) approximation to the MPM (maximizer of the posterior marginals) inference, which is a kind of Bayes inference. In the field of artificial neural networks, this approximation is used to reduce computational cost through the substitution of stochastic binary units with the deterministic continuous value units. However, few reports have quantitatively described the performance of this approximation. Therefore, we have analyzed the approximation performance from a theoretical viewpoint, and have compared our results with the computer simulation.

The technological development of wireless environment has made real-time multimedia communications possible in wireless networks. Many studies have been done on real-time communications in wireless networks in order to overcome a higher bit error rate in wireless channels. However, none of work deals with firm real-time communications which can be applied to multimedia communications. In this paper, we propose an adaptive error correcting scheme for firm real-time multimedia communications in wireless networks in order to maximize the expected net profit. The proposed scheme adaptively selects an error correcting code under the current air state and the message state of a message stream. Throughout simulation results, we show that the suggested scheme provides more profit than single error-correcting code schemes.

In certain computer and communication systems, the significant number of byte errors are not hard errors, but a few transient bit errors confined to byte regions. This kind of byte errors are called spotty byte errors, meaning, not all, but only 2 or 3 random bits, are corrupted in a byte. Especially, the codewords of memory systems which use recent high density wide I/O data semiconductor DRAM chips are prone to this kind of spotty byte errors. This is because, the presence of strong electromagnetic waves in the environment or the bombardment of an energetic particle on a DRAM chip is highly likely to upset more than just one bit stored in that chip. Under this situation, codes capable of correcting single spotty byte errors are suitable for application in semiconductor memory systems. This paper defines a spotty byte error as a random t-bit error confined to a b-bit byte and proposes a class of codes called Single t/b-error Correcting (St/bEC) codes which are capable of correcting single spotty byte errors occurring in computer and communication systems. For the case where the chip data output is 16 bits, i.e., b=16, the S3/16EC code proposed in this paper requires only 16 check bits, that is, only one chip is required for check bits at practical information lengths such as 64, 128 and 256 bits. Furthermore, this S3/16EC code is capable of detecting more than 95% of all single 16-bit byte errors at information length 64 bits.

This letter presents a code which corrects single bit errors in any location of the word as well as l-bit burst errors occurred in an important part of the word. The proposed code is designed by product of the parity check matrix of the l-bit burst error correcting codes and the matrix which converts input unequal errors into equal errors. This letter also demonstrates the evaluation of the code, and presents the extended codes with two-level burst error correcting capabilities by interleaving.

Existing byte error control codes require too many check bits if applied to a memory system that uses recent semiconductor memory chips with wide I/O data such as 16 or 32 bits, i.e., b=16 or 32. On the other hand, semiconductor memory chips are highly vulnerable to random double bit within a memory chip errors when they are used in some applications, such as satellite memory systems. Under this situation, it becomes necessary to design suitable new codes with double bit within a chip error correcting capability for computer memory systems. This correspondence proposes a class of codes called Double bit within a block Error Correcting - Single b-bit byte Error Correcting ((DEC)B-SbEC) codes where block and byte correspond to memory chip and memory sub-array data outputs, respectively. The proposed codes provide protection from both random double bit errors and single sub-array data faults. For most of the practical cases, the (DEC)B-SbEC codes presented in this correspondence have the capability of accommodating the check bits in a single dedicated memory chip.

Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.

This paper presents a class of binary block codes capable of correcting single synchronization errors and single reversal errors with fewer check bits than the existing codes by 3 bits. This also shows a decoding circuit and analyzes its complexity.