In this paper, we present a novel class of long quasi-cyclic low-density parity-check (QC-LDPC) codes. Each of the codes in this class has a structure formed by concatenating single-parity-check codes and QC-LDPC codes of shorter lengths, which allows for efficient, high throughput encoder/decoder implementations. Using a code in this class, we design a forward error correction (FEC) scheme for optical transmission systems and present its high throughput encoder/decoder architecture. In order to demonstrate its feasibility, we implement the architecture on a field programmable gate array (FPGA) platform. We show by both FPGA-based simulations and measurements of an optical transmission system that the FEC scheme can achieve excellent error performance and that there is no significant performance degradation due to the constraint on its structure while getting an efficient, high throughput implementation is feasible.

The performance of cooperative spectrum sensing (CSS) is limited not only by the imperfect sensing channels but also by the imperfect reporting channels. In order to improve the transmission reliability of the reporting channels, an object based cooperative spectrum sensing scheme with best relay (Pe-BRCS) is proposed, in which the best relay is selected by minimizing the total reporting error probability to improve the sensing performance. Numerical results show that, the reduced total reporting error probability and the improved sensing performance can be achieved by the Pe-BRCS scheme.

This paper presents a digitally error-corrected pipeline analog-to-digital converter (ADC) using linearization of incomplete settling errors. A pre-charging technique is used for residue amplifiers in order to reduce the incomplete settling error itself and linearize the input signal dependency of the incomplete settling error. A technique with charge redistribution of divided capacitors is proposed for pre-charging capacitors without any additional reference sources. This linearized settling error is corrected by a first-order error approximation in digital domain with feasible complexity and cost. Simulation results show that the ADC achieves SNDR of 70 dB, SFDR of 79 dB at nyquist input frequency in a 65 nm CMOS process under 1.2 V power supply voltage for 1.2 Vp-p input signal swing. The estimated power consumption of the 12b 200 MS/s pipeline ADC using the proposed digital error correction of incomplete settling errors is 7.6 mW with a small FOM of 22 fJ/conv-step.

In this paper, we develop a novel two-sample test statistic for edge detection in CT image. This test statistic involves the non-parametric estimate of the samples' probability density functions (PDF's) based on the kernel density estimator and the calculation of the mean square error (MSE) distance of the estimated PDF's. In order to extract single-pixel-wide edges, a generic detection scheme cooperated with the non-maximum suppression is also proposed. This new method is applied to a variety of noisy images, and the performance is quantitatively evaluated with edge strength images. The experiments show that the proposed method provides a more effective and robust way of detecting edges in CT image compared with other existing methods.

Cardinality estimation schemes of Radio Frequency IDentification (RFID) tags using Framed Slotted ALOHA (FSA) based protocol are studied in this paper. Not as same as previous estimation schemes, we consider tag cardinality estimation problem under not only detection errors but also capture effect, where a tag's IDentity (ID) might not be detected even in a singleton slot, while it might be identified even in a collision slot due to the fading of wireless channels. Maximum Likelihood (ML) approach is utilized for the estimation of the detection error probability, the capture effect probability, and the tag cardinality. The performance of the proposed method is evaluated under different system parameters via computer simulations to show the method's effectiveness comparing to other conventional approaches.

Turbo equalization is an iterative equalization and decoding technique that can achieve impressive performance gains for communication systems. In this letter, we investigate the turbo equalization method for the decoding of the Davey-MacKay (DM) construction over the IDS-AWGN channels, which indicates a cascaded insertion, deletion, substitution (IDS) channel and an additive white Gaussian noise (AWGN) channel. The inner decoder for the DM construction can be seen as an maximum a-posteriori (MAP) detector. It receives the beliefs generated by the outer LDPC decoder when turbo equalization is used. Two decoding schemes with different kinds of inner decoders, namely hard-input inner decoder and soft-input inner decoder, are investigated. Simulation results show that significant performance gains are obtained for both decoders with respect to the insertion/deletion probability at different SNR values.

Novel joint motion-compensated interpolation using eight-neighbor block motion vectors (8J-MCI) is presented. The proposed method uses bi-directional motion estimation (BME) to obtain the motion vector field of the interpolated frame and adopts motion vectors of the interpolated block and its 8-neighbor blocks to jointly predict the target block. Since the smoothness of the motion vector filed makes the motion vectors of 8-neighbor blocks quite close to the true motion vector of the interpolated block, the proposed algorithm has the better fault-tolerancy than traditional ones. Experiments show that the proposed algorithm outperforms the motion-aligned auto-regressive algorithm (MAAR, one of the state-of-the-art frame rate up-conversion (FRUC) schemes) in terms of the average PSNR for the test image sequence and offers better subjective visual quality.

This paper presents a fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator (DSM), with an analog error cancellation logic circuit, and a digital decimation filter that is fabricated using 0.18-µm CMOS technology. The 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e2). This error can be eliminated using an analog error cancellation logic circuit. In the proposed differential sample-and-hold circuit, low input impedance is presented with feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror. Also, measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3 dB, 69 dB, 10.9 bits, 12.3 mW, and 0.200.21 mm2, respectively, with a bandwidth of 40 kHz, a sampling rate of 10.24 MHz, an OSR of 128 and a supply voltage of 1.8 V.

This paper proposes a novel method to determine a priority for applying selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of application circuits onto coarse-grained reconfigurable architectures (CGRAs). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) of the application circuit. The estimation is based on a weighted sum of the node parameters which characterize impact of the SEU in the node on the output data. This method does not require time-consuming placement-and-routing processes, as well as extensive fault simulations for various triplicating patterns, which allows us to identify the set of nodes to be triplicated for minimizing the vulnerability under given area constraint at the early stage of design flow. Therefore, the proposed method enables us efficient design space exploration of reliability-oriented CGRAs and their applications.

In this letter, we propose an error surface modeling-based segmentalized motion estimation for video coding. We proposed two algorithms previously, one was MBQME [1] and the other is HMBQME [2]. However, these algorithms are not based on locally quadratic MC prediction errors around an integer-pixel motion vector and the hypothesis that the local error plane is a convex function. Therefore, we propose an error surface considered segmentalized modeling algorithm. In this scheme, the tendency of the error surface is first assessed. Using the Sobel operation at the error surface, we classify the error surface region as plain or textured. For plain regions, conventional MBQME is appropriate as the quarter-pixel motion estimation method. For textured regions, we search the additional interpolation points for more accurate modeling. After the interpolation, we perform double precision mathematical modeling so as to find the best motion vector (MV). Experiments show that the proposed scheme has better PSNR performance than conventional modeling algorithms with minimum operation time.

According to the process scaling, radiation-hard devices are becoming sensitive to soft errors caused by Multiple Cell Upset (MCUs). In this paper, the parasitic bipolar effects are utilized to suppress MCUs of the radiation-hard dual-modular flip-flops. Device simulations reveal that a simultaneous flip of redundant latches is suppressed by storing opposite values instead of storing the same value due to its asymmetrical structure. The state of latches becomes a specific value after a particle hit due to the bipolar effects. Spallation neutron irradiation proves that MCUs are effectively suppressed in the D-FF arrays in which adjacent two latches in different FFs store opposite values. The redundant latch structure storing the opposite values is robust to the simultaneous flip.

This paper presents a joint linear processing scheme for two-hop and half-duplex distributed amplify-and-forward (AF) relaying networks with one source, one destination and multiple relays, each having multiple antennas. By using the minimum mean-square error (MMSE) criterion and the Wiener filter principle, the joint relay and destination design with perfect channel state information (CSI) is first formulated as an optimization problem with respect to the relay precoding matrix under the constraint of a total relay transmit power. The constrained optimization with an objective to design the relay block-diagonal matrix is then simplified to an equivalent problem with scalar optimization variables. Next, it is revealed that the scalar-version optimization is convex when the total relay power or the second-hop SNR (signal to noise ratio) is above a certain threshold. The underlying optimization problem, which is non-convex in general, is solved by complementary geometric programming (CGP). The proposed joint relay and destination design with perfect CSI is also extended for practical systems where only the channel mean and covariance matrix are available, leading to a robust processing scheme. Finally, Monte Carlo simulations are undertaken to demonstrate the superior MSE (mean-square error) and SER (symbol error rate) performances of the proposed scheme over the existing relaying method in the case of relatively large second-hop SNR.

Reed-Solomon (RS) code is one of the well-known and widely used error correction codes. Among the components of a hardware RS decoder, the key equation solver (KES) unit occupies a relatively large portion of the hardware. It is important to develop an efficient KES architecture to implement efficient RS decoders. In this paper, a novel polynomial division technique used in the Euclidean algorithm (EA) of the KES is presented which achieves the short critical path delay of one Galois multiplier and one Galois adder. Then a KES architecture with the EA is proposed which is efficient in the sense of the product of area and time.

This paper proposes a scheme for fairness between uplink and downlink in error-prone 802.11 DCF WLANs by differentiating the contention window of AP. While existing schemes consider only collision, the proposed scheme takes into account packet error due to poor channel condition, too. Instead of complex analytical models based on Markov chain processes, a simpler model based on mean value analysis is proposed. It works on 802.11 DCF and so avoids being dependent on TXOP which lacks applicability. A performance evaluation shows that the proposed method can achieve fairness even in error-prone environments without decrease of total throughput when compared with existing schemes.

The Generalized cross-correlation (GCC) method is most commonly used for time delay estimation (TDE). However, the GCC method can result in false peak errors (FPEs) especially at a low signal to noise ratio (SNR). These FPEs significantly degrade TDE, since the estimation error, which is the difference between a true time delay and an estimated time delay, is larger than at least one sampling period. This paper introduces an algorithm that estimates two peaks for two cross-correlation functions using three types of signals such as a reference signal, a delayed signal, and a delayed signal with an additional time delay of half a sampling period. A peak selection algorithm is also proposed in order to identify which peak is closer to the true time delay using subsample TDE methods. This paper presents simulations that compare the algorithms' performance for varying amounts of noise and delay. The proposed algorithms can be seen to display better performance, in terms of the probability of the integer TDE errors, as well as the mean and standard deviation of absolute values of the time delay estimation errors.

A high-speed low-complexity time-multiplexing Reed-Solomon-based forward error correction architecture based on the pipelined truncated inversionless Berlekamp-Massey algorithm is presented in this paper. The proposed architecture has very high speed and very low hardware complexity compared with conventional Reed-Solomon-based forward error correction architectures. Hardware complexity is improved by employing a truncated inverse Berlekamp-Massey algorithm. A high-speed and high-throughput data rate is facilitated by employing a three-parallel processing pipelining technique and modified syndrome computation block. The time-multiplexing method for pipelined truncated inversionless Berlekamp-Massey architecture is used in the parallel Reed-Solomon decoder to reduce hardware complexity. The proposed architecture has been designed and implemented with 90-nm CMOS technology. Synthesis results show that the proposed 16-channel Reed-Solomon-based forward error correction architecture requires 417,600 gates and can operate at 640 MHz to achieve a throughput of 240 Gb/s. The proposed architecture can be readily applied to Reed-Solomon-based forward error correction devices for next-generation short-reach optical communications.

A multiuser precoding algorithm based on matching weighted signal-to-leakage-and-noise ratio (SLNR) is proposed for multiuser MIMO downlink systems. In the proposed algorithm, the matching weight factor is selected based on the effective channel gain, and the leakage power caused by each user is weighted by the factor. The precoding vector is obtained by maximizing the matching weighted SLNR. Simulation results show the superiority of the proposed scheme in terms of bit error rate over the conventional SLNR schemes.

SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a soft-error induced by radiation. Techniques for designing dependable circuits, such as triple modular redundancy (TMR) with scrubbing, have been studied extensively. However, currently available evaluation techniques that can be used to check the dependability of these circuits are inadequate. Further, their results are restrictive because they do not represent the result in terms of general reliability indicator to decide whether the circuit is dependable. In this paper, we propose an evaluation method that provides results in terms of the realistic failure in time (FIT) by using reconfiguration-based fault-injection analysis. Current fault-injection analyses do not consider fault accumulation, and hence, they are not suitable for evaluating the dependability of a circuit such as a TMR circuit. Therefore, we configure an evaluation system that can handle fault-accumulation by using frame-based partial reconfiguration and the bootstrap method. By using the proposed method, we successfully evaluated a TMR circuit and could discuss the result in terms of realistic FIT data. Our method can evaluate the dependability of an actual system, and help with the tuning and selection in dependable system design.

In this paper, we propose a wireless network coding diversity technique based on hybrid amplify-and-forward/decode-and-forward relay method employing adaptive power control for two-hop wireless networks in order to improve relay node position flexibility. Wireless network coding diversity based on hybrid relay method selects either modulation symbol level wireless network coding diversity or bit sequence level wireless network coding diversity as its wireless network coding diversity scheme according to the cyclic redundancy check result at the relay node. Moreover, the adaptive power control scheme proposed here controls the relay node's transmit power according to its position. Computer simulations verify that wireless network coding diversity based on hybrid relay method employing the adaptive power control scheme can expand the area wherein the relay node can be located while satisfying the required communication quality by 4.56 times compared to the conventional wireless network coding diversity scheme. Therefore, we confirm that our proposed scheme can increase relay node position flexibility.

Recently, the DVS (Dynamic Voltage Scaling) method has been aggressively applied to processors with Razor Flip-Flops. With Razor FF detecting setup errors, the supply voltage in these processors is down-scaled to a near critical setup timing level for a maximum power consumption reduction. However, the conventional Razor and DVS combinations cannot tolerate well error rate variations caused by IR-drops and environment changes. At the near critical setup timing point, even a small error rate change will result in sharp performance degradation. In this paper, we propose RazorProtector, a DVS application method based on a redundant data-path which uses a multi-cycle redundant calculation to shorten the recovery penalty after a setup error occurrence. A dynamic redundancy-adapting scheme is also given to use effectively the designed redundant data-path based on a study of the program, device and error rate characteristics. Our results show that RazorProtector with the adaptive redundancy architecture can, compared to the traditional DVS method with Razor FF, under a large setup rate caused by a 10% unwanted voltage drop, reduce EDP up to 78% at 100 µs/V, 88% at 200 µs/V voltage scaling slope.