A new graphic and display processor, which is suitable for high-performance car navigation systems or next-generation ITS mobile terminals, has been developed. The performance bottleneck of conventional consumer graphic systems exists not only in the rendering performance of the graphic processor itself, but also in CPU-capability and CPU-bus bandwidth. To release this latter bottleneck, the new processor has Controller/DSP Unit and FPU for graphic-macro-command parsing and geometric operations, respectively, which used to be the CPU tasks and occupy some amount of CPU-bus bandwidth to transfer their results. The architecture of the new processor is organized so as to carry out macro-pipelined operations of graphic and display processing smoothly. One of the features of this processor is having special hardware, Polygon-Engine and Short-Vector-Accelerator, for the rapid rendering of 2D maps, where complex polygons and short line-segments are the dominant objects to be rendered. Another feature is the hardware support of multi-layer/window display with alpha-blend overlapping. This function and additional video processing capability, such as MPEG4 decoding, would be useful in the next generation intelligent terminals. The processor LSI has been successfully fabricated by using 0.18 µm standard CMOS technology. More than five million transistors are implemented on this chip. The peak rendering speed of this processor has been measured as 200 Mpixel/s at 133 MHz processor internal clock frequency. Other results of the graphic system evaluation have demonstrated that this new processor has appropriately high performance and useful functions for the next generation mobile terminals.

A 23.3 mm2 32 Mb embedded DRAM (eDRAM) macro has been fabricated using 0.18 µm triple-well 4-metal embedded DRAM process technology to realize an accelerated 3-D graphics controller. The array architecture, using a dual-port sense amplifier, achieves the column access latency of two cycles at 222 MHz and a peak data rate of 14.2 4 GB/s at 4 macros. The process cost has been kept low by using VT-MOS circuit technology and taking advantage of a characteristic of dual-gate oxide process technology. A tRAC of 11.6 ns at 2.0 V is achieved using a 'pre-detect redundancy' circuit.

A base model should be transmitted first in progressive transmission schemes, and its transmission delay dominates initiation time for rendering. To reduce the initiation time, we restructure the base model to transmit visible vertices and triangles for some specific viewpoints first, and therefore clients can start rendering when parts of model file are received. Simulation results show that only 37.4% - 51.3% of model file are required to start rendering, and hence the initiation time is significantly reduced.

This paper describes a kind of 3D graphics geometry processor architecture for high performance/cost 3D graphics, its application to a real chip, and the results of performance evaluation. In order to establish the high speed geometry processing, dedicated hardware is introduced for accelerating special operations, such as power calculations, clip tests, and program address generation. The dedicated hardware consists of a modified floating-point multiplier in a four-parallel SIMD processing core, a clip test unit, and an internal program address generation scheme optimized to geometry processing mode. Special instructions corresponding to the dedicated schemes are also defined and added. The parallelism of the SIMD core is adjusted to a geometry data structure. Employing dedicated hardware and software significantly accelerates these complicated operations deriving from geometry algorithms. The collaboration of the hardware design and the software design considerably reduces instruction step counts for complex processing. Two kinds of program are dealt with in the proposed architecture. One is a special case program containing few conditional jump instructions, and the other is a general case program combining many program routines. The proposed program address generation scheme provides the automatic selection of a program optimized to each geometry processing mode. By this program address generation scheme and the program types, the frequency of the conditional jump operations, that usually disturb a pipeline operation, are minimized under practical use. Additionally, the programmable design and this program address generation scheme facilitate the load balancing of the geometry calculations with the CPU. A programmable geometry processor was fabricated by using 0.35 µm CMOS process as an application of this architecture. One point three million transistors are integrated in a 11.84 12.07 mm2 die. The increase of the gate counts for all the dedicated hardware is a total of 24 K gates and is approximately only a 7.4% increase of the total gate count. This chip operates at 150 MHz, and achieves the processing performance of 5.8 M vertex/sec. The result shows that the proposed programmable architecture (ESIMD: Enhanced SIMD) is 2.3 times more cost effective than a programmable geometry LSI reported previously.

In the field of computer graphics (CG), some adaptive methods have been proposed in order to make CG images more real in relatively low computational cost. As one of such adaptive methods, in this paper, an adaptive method will be proposed for detection of edges and approximation of surfaces in the use of the so-called automatic differentiation. In the proposed method a CG image with high quality can be generated in suitable computational cost. In this paper, three cases will be considered. The first is an adaptive distributed ray tracing which can adaptively generate anti-aliased CG images in suitable computational cost. The second is a high quality triangular meshing, which guarantees accuracy of the generated meshes according to shape of given surface in suitable computational cost. The last case is used in the so-called radiosity method.

Antialiased is one of challenging problems to be solved for the high fidelity image synthesis in 3D graphics. In this paper a rasterization processor which is capable of single-pass full-screen antialiasing is presented. To implement a H/W accelerated single-pass antialiased rasterization processor at the reasonable H/W cost and minimized processing performance degradation, our work is mainly focused on the efficient H/W implementation of a modified version of the A-buffer algorithm. For the efficient handling of partial-pixel fragments of the rasterization phase, a new partial-pixel-merging scheme and a simple and efficient new dynamic memory management scheme are proposed. For the final blending of partial-pixels without loss of generality, a parallel subpixel blender is introduced. To study the feasibility of the proposed rasterization processor as a practical rasterization processor, a prototype processor has been designed using a 0.35 µm EML technology. It operates 100 MHz @3.3 V and has the rendering performance from 25M to 80M pixel-fragments/sec depending on the scene complexity.

A VLIW (Very Long Instruction Word) architecture with a new code compaction method has been proposed. For a 3D-geometry processor, we consider two types of 2-issue VLIW architectures, the floating-point execution accelerating VLIW (FP-VLIW) and the data-move enhancing VLIW (MV-VLIW) architectures, as expansions of a Single-Streaming Single Instruction, Multiple Data (SS-SIMD) architecture. To solve the code bloat problem which is common to VLIW architectures, the proposed method makes it possible to compact original codes into the VLIW codes by software tools and decompact the VLIW codes by a simple hardware decompactor composed of an instruction swap circuit on a chip. Speeds and code densities of the two VLIWs with the code compaction are compared to the SS-SIMD with the same instruction set and the same building blocks. The FP-VLIW shows the fastest speed performance in the evaluation results of the viewperf CDRS-03 benchmark programs. It is 36% faster than the SS-SIMD used as reference. The proposed compaction method keeps the 95% code density of the SS-SIMD. One test program shows that the code density of the MV-VLIW is higher than that of the SS-SIMD. This result demonstrates that the merit of compacting nops can be greater than the VLIW penalty. The FP-VLIW architecture with the code compaction achieves 1.36 times the speed performance without significant code-density deterioration.

We present a scalable parallel rasterizer based on our interleaved scanline rasterization. The sorting overhead of a conventional scanline-based parallel rendering approach has been studied and removed by implementing a scanline assignment hardware. All advantages of the scanline-based parallel rendering are kept such that a good scalability and a small memory usage are achieved. Our architecture is evaluated precisely by a discrete event-based simulation, and the rendering performance and utilization are shown for a various number of rasterizers. The simulation results show more than 8 Mtriangles/s of performance with 64 rasterization engines running at 10 MHz.

In this paper, we propose a realtime concatenation technique between basic skeletal motions obtained by the motion capture technique and etc. to generate a lifelike behavior for a humanoid character (avatar). We execute several experiments to show the advantage and the property of our technique and also report the results. Finally, we describe our applied system called WonderSpace which leads participants to the exciting and attractive virtual worlds with humanoid characters in cyberspace. Our concatenation technique has the following features: (1) based on a blending method between a preceding motion and a succeeding motion by a transition function, (2) realizing "smooth transition," "monotone transition," and "equivalent transition" by the transition function called paste function, (3) generating a connecting interval by making the backward and forward predictions for the preceding and succeeding motions, (4) executing the prediction under the hypothesis of "the smooth stopping state" or "the state of connecting motion", (5) controlling the prediction intervals by the parameter indicating the importance of the motion, and (6) realizing realtime calculation.

This paper presents a new data hiding scheme under fractal image generation via Fourier filtering method for Computer Graphics (CG) applications. The data hiding operations are achieved in the frequency domain and a method similar to QAM used in digital communication is introduced for efficient embedding in order to explore both phase and amplitude components simultaneously. Consequently, this scheme enables us not only to generate a natural terrain surface without loss of fractalness analogous to the conventional scheme, but also to embed larger amounts of data into an image depending on the fractal dimension. This scheme ensures the correct decoding of the embedded data under lossy data compression such as JPEG by controlling the quantization exponent used in the embedding process.

This paper presents a new data hiding scheme via steganographic image transformation, which is different from conventional data hiding techniques. The transformation is achieved in the frequency domain and the concept of Fourier filtering method is used. An input image is transformed into a fractal image, which can be used in Computer Graphic (CG) applications. One of the main advantages of this scheme is the amount of data to be hidden (embedded) is equal to that of the host signal (generated fractal image) while it is in general limited in the conventional data hiding schemes. Also both the opened fractal image and the hidden original one can be properly used depending on the situation. Unauthorized users will not notice the "secret" original image behind the fractal image, but even if they know that there is a hidden image it will be difficult for them to estimate the original image from the transformed image. Only authorized users who know the proper keys can regenerate the original image. The proposed method is applicable not only as a security tool for multimedia contents on web pages but also as a steganographic secret communication method through fractal images.

Cursor RAMs have been composed of two memory planes. A cursor pattern is stored in these planes with 2-bit data depth. While the pixel port requires data from both planes at the same time, the MPU port accesses either one of the planes at a time. Since the address space is defined differently between the ports, conventional cursor RAMs could not have dealt with these different access ways at real time. This paper proposes a dual port cursor RAM with a dynamic data alignment architecture. The architecture processes the different access ways at real time, and reduces a large amount of control circuitry. Conventional cursor RAMs have been organized with a single port memory because dual port memory cells have been large. We have applied the port swap architecture which has reduced the cell size. The control block is further simplified because the controller no longer emulate a dual port memory. The cursor RAM with these architectures is fabricated with a double metal 0. 5 µm CMOS process technology. The active area is 1. 51. 6 mm2 including a couple of shift registers and a control block. It operates up to 263 MHz at the supply voltage of 3. 3 V.

This paper proposes a dual port color palette SRAM using a single bit line cell. Since the single bit line cell consists of fewer bit lines and transistors than standard dual port cells, it is able to reduce the area. However, the cell has had a problem in writing a high level. The port swap architecture solves the problem without any special mechanism such as a boot strap. In the architecture, each of two bit lines is assigned to the read/write MPU port and the read only pixel port, respectively. When writing a low level, the MPU port uses pre-assigned bit line. On the other hand, when writing a high level, the MPU port uses the bit line assigned to the pixel port by a swap operation. During the swapping, the pixel port continues the read operation by using the bit line assigned to the MPU port. A color palette using this architecture is fabricated with a 0. 5 µm CMOS process technology. The memory cell size reduces by up to 43% compared with standard dual port cells. The color palette is able to supply the pixel data at 300 MHz at the supply voltage of 3.3 V. This speed is enough to support the practical highest resolution monitors in the world.

Increasingly, 3D Graphics is becoming the main stream feature rather than the early adopters unique advantage in PC platform. In such circumstances, most of the graphics chips focus on the acceleration of the rendering capabilities. However, there are very few or almost no attempts made for the acceleration of the geometry process. This universal 3D graphics geometry processor offers a unique and optimized performance advantage for such 3D geometry calculations. By offloading such operations from the CPU, this 3D graphics geometry processor (hereinafter called 3DGP) delivers a well balanced 3D graphics acceleration environment in the PC.

This paper describes the 'Procyon' processor which is to be used for geometry processing. The objective of this processor is to provide a high performance geometry processor to support next generation 3D graphics such as game and CAD applications. The Procyon processor is a four parallel VLIW processor which makes hardware logic simple. We are pursuing performance improvement by compiler optimization. Procyon has a unique feature called 'Software bypass' as well as special hardware to support 3D graphics processing. Software bypass enables the compiler to make accesses to data on hardware bypass lines. By using this information, the compiler can schedule instructions much more freely and generates efficient VLIW code. Other features of Procyon are multiply-add-accumulate instruction, SIMD instructions and clipping instructions. Procyon VLIW code is held in compacted form, which improves memory performance. A program development environment, such as a pipeline simulator and an assembly code parallelizer, is also prepared for system and application programmers. Preliminary simulation results demonstrate that a performance of 2. 6 M polygons per second at 125 MHz Procyon is attained.

A method for generating circles and arcs is the general class of algorithms known as digital differential analyzers (DDA). However, there are some defects in the DDA algorithms. In this paper, a discrete form of the equation of a circle is revised and the defects in the DDA are removed.

We implement a graphical interface that automatically transforms a figure input by a mouse into a regular figure which the system infers is the closest to the input. The difficulty lies in the fact that the classes into which the input is to be classified have inclusion relations, which prohibit us from using a simple distance criterion. In this letter, we show that this problem can be resolved by introducing the geometric AIC.

We describe an algorithm for efficiently compositing partial images generated during parallel volume rendering on a distributed memory parallel computer. In this object space partitioning algorithm, each PE is assigned to several subvolumes where each subvolume has a corresponding local frame buffer. After volume rendering is performed independently for each subvolume, the partial images stored in the local frame buffers are combined to generate a complete image. During this compositing process, the communication of partial image data between the PEs is kept minimal by assigning PEs to subvolumes in an interleaved manner. This assignment makes possible a reduction in communication in the axis direction in which there is the most communication. Experimental results indicate that a 9% to 35% reduction in the total rendering time can be attained with no additional data structures and no memory overhead.

The advantages of DRAM-logic integration were demonstrated through a comparison with a conventional separate-chip architecture. Although the available DRAM capacity is restricted by chip size, the integration provides a high throughput and low I/O-power dissipation due to a large number of on-chip I/O lines with small load capacitance. These features result in smaller chip counts as well as lower power dissipation for systems requiring high data throughput and having relatively small memory capacity. The chip count and I/O-power dissipation were formulated for multimedia systems. For the 3-D computer graphics system with a frame of 12801024 pixels requiring a 60-Mbit memory capacity and a 4.8-Gbyte/s throughput, DRAM-logic integration enabled a 1/12 smaller chip count and 1/10 smaller I/O-power dissipation. For the 200-MIPS hand-held portable computing system that had a 16-Mbit memory capacity and required a 416-Mbyte/s throughput, DRAM-logic integration enabled a 1/4 smaller chip count and 1/17 smaller I/O-power dissipation. In addition, innovative architectures that enhance the advantages of DRAM-logic integration were discussed. Pipeline access for a DRAM macro having a cascaded multi-bank structure, an on-chip cache DRAM, and parallel processing with a reduced supply voltage were introduced.

Producing realistic images and animations of flames is one of the most interesting subjects in the field of computer graphics. In a recent paper, we described a two-dimensional particle-based visual method of simulating flames. In the present paper, we first extend the simulation method, without losing any of its desirable features, in such a way that it functions in three-dimensional space. We then present an efficient method of producing an image of the scene, including flames acting as volume light sources, which normally requires a large amount of computing time in the usual simulation approaches. Finally, we demonstrate the capabilities of our visual simulation method by showing sample images generated by it, which are excerpted from an animation.