We have developed 100 nm node CMOS technology, consisting of a 65 nm gate length and a 1.6 nm gate oxide thickness. The major transistor design issue is how to maintain drive current at supply voltage of only 1.0 V, while suppressing standby leakage current to a practical level for system-on-a-chip applications. In order to obtain thinner electrical equivalent oxide thickness with well-suppressed gate leakage current, we have adopted radical nitridation and poly-SiGe. We have also utilized low-energy ion-implantation, low-temperature CVD, and spike RTA technology to overcome the short channel effect. With supply voltage of 1.0 V, our generic transistor shows the drive current of 520/196 µA/µm with the off current of 0.5 nA/µm. We also designed high-speed (Ioff=5 nA/µm), ultrahigh-speed (Ioff=30 nA/µm) transistors, and low-standby power (Ioff=5 pA/µm), all of which can be deployed on the same chip.

Breakthroughs in crystal growth and conductivity control of nitride semiconductors during last two decades have led to such developments as high-brightness blue and green light-emitting diodes and long-lived violet laser diodes and so on. All of these nitride-based devices are robust and the most environmentally-friendly ones available. They enable us to save tremendous amount of energy and will be key devices in advanced information technology. Further progress in the area of crystal growth and device engineering will open up new frontier devices based on nitride semiconductors. In this paper, the evolution of nitride-based light-emitting devices is reviewed and the key issues, which must be addressed for nitrides to be fully developed, are discussed.

We have manufactured large-scaled highly reliable MNOS EEPROMs over the last twenty years. In particular, at the present time, the smart-card microcontroller incorporating an embedded 32-kB MNOS EEPROM is rapidly expanding the markets for mobile applications. It might be said that we have established the conventional MNOS nonvolatile semiconductor memory technology. This paper describes the device design concepts of the MNOS memory, which include the optimization and control of the tunnel oxide film thickness (1.8 nm), and the scaling guideline that considers the charge distribution in the trapping nitride film. We have developed a high-performance MONOS structure and have not found any failure due to the MONOS devices in high-density EEPROM products during 10-year data retention tests after 105 erase/write cycles. The future development of this highly reliable MNOS-type memory will be focussed on the high-density cell structure and high-speed programming method. Recently, some promising ideas for utilizing an MNOS-type memory device, such as 1-Tr/bit cell for byte-erasable full-featured EEPROMs and 2-bit/Tr cell for flash EEPROMs have been proposed. We are convinced that MNOS technology will advance into the area of nonvolatile semiconductor memories because of its high reliability and high yield of products.

A tunnel film(9 nm thick) formed by a rapid thermal oxidation in dry oxygen-rapid thermal nitridation in NH3-rapid thermal oxynitridation in N2O (ONN) sequence is applied to a stacked-gate flash memory cell, in which writing and erasing are carried out by Fowler-Nordheim tunneling at a drain and at a channel, respectively. The writing, erasing, endurance, disturbance and retention characteristics of the memory cells with ONN tunnel films are, for the first time, compared to those of the memory cells with conventional tunnel films such as dry oxide, N2O-oxynitride and reoxidized nitrided oxide tunnel films. No significant difference of the writing and erasing characteristics was observed among the memory cells with the various tunnel films. However, the amount of Vth window narrowing in the endurance characteristics of the memory cells with ONN (-12.9%) and reoxidized nitrided oxide(-11.4%) tunnel films were much smaller than those of the memory cells with RTO(-34.0%) and NO (-38.2%) after 106 write/erase cycles. Furthermore, the decrease in Vth in the drain disturbance characteristics of the memory cells with ONN tunnel films (21.2%) after weak electron-ejecting stress of 105 cycles was smaller than those of the memory cells with the other films(51.4-64.4%). The retention characteristics of the memory cells with ONN tunnel films under the thermal stress of 200, 5.9105 sec were superior(ΔVth=-2.1%) to those of the memory cells with the other films(ΔVth=-5.4 - -8.2%). The reasons of these findings are because ONN films exhibit smaller number of charge traps and interface states induced by write/erase cycle stress, and suppress leakage curent stimulated by the weak electron-ejecting bias and the thermal stress, compared to the dry oxide, the N2O-oxynitride and the reoxidized nitrided oxide. ONN films are found to be suitable for use as tunnel films of fiash memory cells.

A copper(Cu) thick film conductor containing glass and metal oxide for aluminum niride(AlN) substrate was developed. The conductor showed adhesion strength and reliability which were almost comparable to those of Ag-Pd conductors and also had good solder wettability and erosion properties. The Cu conductors must be fired in a nitrogen atmosphere containing oxygen gas. When they were fired under a low oxygen concentration, the gasses thermally decomposed and their properties changed which meant that the molten gasses could not flow smoothly to the AlN surface, so adhesion strength decreased. On the other hand, under high oxygen concentration, the adhesion strength increased because the thermal decomposition and property changes were suppressed. However, poorer solder wettability was brought about because copper was oxidized. Metal oxide added to the conductor could improve the wettability without decreasing the adhesion strength, even if it was fired at the higher oxygen concentration. Suitable metal oxides were CdO, Co3O5 and Fe2O3.

A contact-less cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim (F-N) tunneling, has been developed for single 3 V power-supply 64 Mbit and future flash memories. A 1.50 µm2 cell area is obtained by using 0.4 µm technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) an advanced rapid thermal process for 7.5 nm-thick tunnel-oxynitride. The internal-voltages used for PROGRAM and ERASE are8 V and 12 V, respectively. The use of low positive internal-voltages results in reducing total process step numbers compared with reported memory cells. The HiCR cell also realizes low power and fast random access with a single 3 V power-supply.

Phosphorus-doped amorphous or polycrystalline silicon can yield a conformal, low resistance, thermallystable plug for the high-aspect-ratio, sub-half-micron contactholes found in current development prototypes of future 64 and 256 Mega-bit DRAMs. When directly contacted to a silicide layer, however, such as WSix found in polycide gate or bit line metallization/contact structures, the outdiffusion of phosphorus from the doped-silicon layer into the silicide can occur, resulting in an increase in resistance. The characteristics of both the doped-silicon and WSix layers influence the outdiffusion. The grain size of the doped silicon appears to control diffusion at the WSix/doped-silicon interface while the transition of WSix from an as-deposited amorphous to a post-annealed polycrystalline state appears to help cause uniform phosphorus diffusion throughout the silicide film. The results of phosphorus pre-doping of the silicide to reduce the effects of outdiffusion are dependent upon the relative material volumes and interfacial areas of the layers. Due to the effectiveness of the TiN barrier layer/Ti contact layer structure used in Al-based contacts, Ti and TiN were evaluated on their ability to prevent phosphorus outdiffusion. Ti reacts easily with doped silicon and to some extent with WSix, thereby allowing phosphorus to outdiffuse through the TiSix into the overlying WSix. TiN, however, is very effective in preventing phosphorus outdiffusion and preserving polycide interface smoothness. A WSix/TiN/Ti metallization layer on an in situ-doped (ISD) silicon layer with ISD silicon-plugged contactholes yields contact resistances comparable to P+-implanted or non-implanted WSix layers on similar ISD layers/plugs for contact sizes greater than approximately 0.5 µm but for contacts of 0.4 µm or below the trend in contact resistance is lowest for the polycide with TiN barrier/Ti contact interlayers. A 20 nm-thick TiN film retains its barrier characteristics even after a 4-hour 850 anneal and is applicable to the silicide-on-doped-silicon structures of future DRAM and other ULSI devices.

Silicon nitride (SiNx) films have been deposited at lower substrate temperatures (500) by direct (without mercury-sensitization) photo-chemical vapor deposition (photo-CVD) using SiH4 and NH3 with a low-pressure mercury lamp. Films deposited at around 350 have a polymeric structure such as (Si(NH)2)n. Films deposited at 500 were close to stoichiometric Si3N4 with a slight amount of hydrogen. The refractive index and the dielectric constant of films deposited at 500 became almost equal to the values of thermally synthesized Si3N4. The resistivity was as high as 51016 Ωcm. The minimum density of interface states in Al/SiNx/Si MIS (metal-insulator-semiconductor) diodes was estimated to be 91010 cm-2eV-1 by a quasi-static capacitance-voltage measurement. For SiNx films deposited at 300, the density of interface states, which was in the order of 1011 cm-2eV-1 as deposited, decreased by a rapid thermal anneal after the deposition. For Al/SiNx/InP MIS diodes, it was 31011 cm-2eV-1 by high-frequency capacitance-voltage measurements. Direct photo-CVD for SiNx films is promising for low-temperature formation of a gate insulator.

Plasmaless etching using ClF3 gas has been investigated on nitride films with different composition. For the sputter deposited and thermally grown silicon nitride films containing no hydrogen, the etch rate increases and the activation energy decreases with increase of the composition ratio of silicon to nitrogen between 0.75 and 1.3. This fact indicates that the etching is likely to proceed through the reaction between Si and ClF3. The native oxide on the silicon-nitride films can also be removed with ClF3 gas. Ultra-violet light irradiation from a low pressure mercury lamp remarkably accelerates the removal of the native oxide and the etch rate of the thermally grown silicon-nitride films. For the plasma deposited films, the etch rate is strongly accelerate with increasing hydrogen content in the films, but the activation energy hardly depends on the bounded hydrogen in the films, consistent with the results for Si etching.