In this paper, a balance operation Transimpedance Amplifier (TIA) with low-noise has been implemented for optical receivers in 130 nm SiGe BiCMOS Technology, in which the optimal tradeoff emitter current density and the location of high-frequency noise corner were analyzed for acquiring low-noise performance. The Auto-Zero Feedback Loop (AZFL) without introducing unnecessary noises at input of the TIA, the tail current sink with high symmetries and the balance operation TIA with the shared output of Operational Amplifier (OpAmp) in AZFL were designed to keep balanced operation for the TIA. Moreover, cascode and shunt-feedback were also employed to expanding bandwidth and decreasing input referred noise. Besides, the formula for calculating high-frequency noise corner in Heterojunction Bipolar Transistor (HBT) TIA with shunt-feedback was derived. The electrical measurement was performed to validate the notions described in this work, appearing 9.6 pA/√Hz of input referred noise current Power Spectral Density (PSD), balance operation (VIN1=896mV, VIN2=896mV, VOUT1=1.978V, VOUT2=1.979V), bandwidth of 32GHz, overall transimpedance gain of 68.6dBΩ, a total 117mW power consumption and chip area of 484µm × 486µm.

To address the bandwidth bottleneck that exists between LSI chips, we have proposed a novel, high-sensitivity receiver circuit for differential optical transmission on a silicon optical interposer. Both anodes and cathodes of the differential photodiodes (PDs) were designed to be connected to a transimpedance amplifier (TIA) through coupling capacitors. Reverse bias voltage was applied to each of the differential PDs through load resistance. The proposed receiver circuit achieved double the current signal amplitude of conventional differential receiver circuits. The frequency response of the receiver circuit was analyzed using its equivalent circuit, wherein the temperature dependence of the PD was implemented. The optimal load resistances of the PDs were determined to be 5kΩ by considering the tradeoff between the frequency response and bias voltage drop. A small dark current of the PD was important to reduce the voltage drop, but the bandwidth degradation was negligible if the dark current at room temperature was below 1µA. The proposed circuit achieved 3-dB bandwidths of 18.9 GHz at 25°C and 13.7 GHz at 85°C. Clear eye openings in the TIA output waveforms for 25-Gbps 27-1 pseudorandom binary sequence signals were obtained at both temperatures.

In this paper, the analog code modulation characteristics of distributed-based transversal filters (DTFs) suitable for use in spectrally encoded CDMA systems are presented. The DTF is verified as an appropriate method to use in high-speed CDMA systems as opposed to previously proposed methods, which are intended for Direct Sequence (DS) CDMA systems. The large degree of freedom of DTF design permits controlling the filter pulse response to generate well specified temporal phase-coded signals. A decoder structure that performs bipolar detection of user subbands giving rise to a Spectral-Amplitude Encoded CDMA system is considered. Practical implementations require truncating the spreading signals by a time window of duration equal to the span time of the tapped delay line. Filter functions are chosen to demodulate the matched channel and achieve improved user interference rejection avoiding the need for transversal filters featuring a large number of taps. As a proof-of-concept of the electronic SAE scheme, practical circuit designs are developed at low speeds (3-dB point at 1 GHz) demonstrating the viability of the proposal.

To meet the demand for continuous increase in data traffic, full usage of polarization freedom of light is becoming inevitable in the next-generation optical communication and datacenter networks. In particular, Stokes-vector modulation direct-detection (SVM-DD) formats are expected as potentially cost-effective method to transmit multi-level signals without using costly coherent transceivers in the short-reach links. For the SVM-DD formats to be practical, both the transmitter and receiver need to be substantially simpler, smaller, and lower-cost as compared to coherent counterparts. To this end, we have recently proposed and demonstrated novel SV modulator and receiver circuits realized on monolithic InP platforms. With compact non-interferometric configurations, relatively simple fabrication procedures, and compatibility with other active photonic components, the proposed devices should be attractive candidate in realizing low-cost monolithic transceivers for SVM formats. In this paper, we review our approaches as well as recent progresses and provide future prospects.

We present an 82.5GS/s over-sampling based burst-mode clock and data recovery (BM-CDR) IC chip-set comprising an 82.5GS/s over-sampling IC using 8×10.3GHz multi-phase clocks and a dual-rate data selector logic IC to realize the 10.3Gb/s and 1.25Gb/s dual-rate burst-mode fast-lock operation required for 10-Gigabit based fiber-to-the-x (FTTx) services supported by 10-Gigabit Ethernet passive optical network (10G-EPON) systems. As the key issue for designing the proposed 82.5GS/s BM-CDR, a fresh study of the optimum number of multi-phase clocks, which is equivalent to the sampling resolution, is undertaken, and details of the 10.3Gb/s cum 1.25/Gb/s dual-rate optimum phase data selection logic based on a blind phase decision algorithm, which can realize a full single-platform dual-rate BM-CDR, ate also presented. By using the power of the proposed 82.5GS/s over-sampling BM-CDR in cooperation with our dual-rate burst-mode optical receiver, we further demonstrated that a short dual-rate and burst-mode preamble of 256ns supporting receiver settling and CDR recovery times was successfully achieved, while obtaining high receiver sensitivities of -31.6dBm at 10.3Gb/s and -34.6dBm at 1.25Gb/s and a high pulse-width distortion tolerance of +/-0.53UI, which are superior to the 10G-EPON standard.

This paper presents a 44 Gbit/s Transimpedance Amplifier (TIA) with wide-dynamic range and high-linearity for optical receiver fabricated in 130 nm BiCMOS technology. The TIA has the features of 67dBΩ overall transimpedance gain, a bandwidth of 28GHz, 10pA/√Hz of Input Referred Noise Current Power Spectral Density (IRNCPSD), and a power consumption of 95mW from a 2.5V supply. The Total Harmonic Distortion (THD) is less than 5% for a differential input current up to 2.63mApp, when the static input current is 0.1mA.

This paper describes a blind frequency offset estimator (FOE) with wide frequency range for coherent quadrature amplitude modulation (QAM) receivers. The FOE combines a spectrum-based frequency offset estimation algorithm as a coarse estimator with a frequency offset estimation algorithm using the periodogram as a fine estimator. To establish our design methodology, each block of the FOE is rigorously analyzed by using formulas and the minimum fast Fourier transform (FFT) size that generates a frequency spectrum for both the coarse and fine estimators is determined. The coarse estimator's main feature is that all estimation processes are carried out in the frequency domain, which yields convergence more than five times faster than that of conventional estimators. The estimation frequency range of the entire FOE is more than 1.8 times wider than that of conventional FOEs. Experiments on coherent optical 64-ary QAM (64-QAM) reveal that frequency offset estimation can be achieved under a frequency offset value greater than the highest value of the conventional estimation range.

To realize economical optical burst signal receivers for the Optical Network Unit (ONU) of the Ethernet Optical Switched Access Network (E-OSAN), we previously implemented optical burst receivers with AC-coupling and DC-coupling using off-the-shelf components, and showed that the former offers better performance. This paper proposes a new optical burst signal receiver that uses the transfer function, Gn(s) = 1-Hn(s), where Hn(s) denotes a Bessel filter transfer function of order n. We also present a method for designing the proposed receiver and clarify that it has better performance than the conventional AC-coupling one. We then present an LCR circuit synthesis of Gn(s), which is necessary to actually implement a burst receiver based on the proposal.

In this paper, a 10-Gb/s CMOS optical receiver analog front-end is designed and implemented in 0.13-µm CMOS technology. An optical receiver analog front-end includes a pre-amplifier and a post amplifier. To ensure 10-Gb/s operation, the effect of inherent photodiode parasitic capacitance should be suppressed. Thus, an advanced common-gate stage is exploited as the input stage of pre amplifier. To enhance the bandwidth without a passive inductor, a new post amplifier with active feedback and negative capacitance compensation techniques is proposed. A prototype chip has 98-dBΩ of trans-impedance gain (ZT), corresponding 40-dB input dynamic range (5-µA to 500-µA) and minimum allowable input current (5-µA). Also, the receiver achieves the bandwidth of 7.5-GHz for 0.25-pF photodiode parasitic capacitance, and the measured optical sensitivity equals -18-dBm for 10-12 bit error rate (BER).

The performance of a new APSK receiver is analyzed using numerical simulation. The proposed receiver eliminates the penalty caused by SPM-induced phase-shift of optical pulses by employing three sub-modules and an amplitude-pattern controlled switch for each DPSK tributary. The interplay between SPM, IXPM, and XPM determines the performance of the proposed receiver for single-channel and WDM transmission.

This article addresses the problem of designing and implementing multigigabit post-detection filters for application in optical communication systems using optical soliton pulses. The designed filters have the main advantages of full integration, electrically adjustable frequency response and active input and output impedance match.

12-channel DC to 622-Mbit/s/ch optical transmitter and receiver have been developed for high-capacity and rather long (about 100 m) bit-parallel raw data transmission in intra- and inter-cabinet interconnection of large-scale switching, routing and computing system. Bit-parallel raw data transmission is done by using a bit-by-bit operational automatic decision threshold control receiver circuit with a DC-coupled configuration, the pin-PDs with their anodes and cathodes separated in a channel-by-channel manner, and a receiver preamplifier with a low-pass filter. The transmitter consists of a 12-channel LD sub-assembly unit and a LD driver LSI. The LD sub-assembly unit consists of a 12-channel array of high temperature characteristic 1.3-µm planar buried hetero-structure (PBH) LDs and 62.5/125 graded-index multi-mode fibers (GI62.5 MMFs). The 1.3-µm PBH LDs and the GI62.5 MMFs are optically coupled by passively visual alignment technology on the Si V-groove. The receiver consists of a 12-channel pin-PD sub-assembly unit and a receiver LSI. The pin-PD sub-assembly unit consist of a 12-channel array of pin-PDs and GI62.5 MMFs. They are optically coupled by using a flip-chip bonding on the Si V-groove. The transmitter and receiver each have eleven data channels and one clock channel. The size is as small as 3.6 cc for each modules, and the power consumptions are 1.7 W (transmitter) and 1.35 W (receiver). They transmitted a bit-parallel raw data through a 100-meter ribbon of GI62.5 MMFs in an ambient temperature range of 0-70C. They provide a synchronous PECL interface parallel link for with a 3.3-V single power supply.

10-Gbit/s monolithic receiver OEIC's for 1.55-µm optical transmission systems were fabricated using a stacked layer structure of p-i-n photodiodes and HEMT's grown on InP substrates by single-step MOVPE. A receiver OEIC with a large O/E conversion factor was obtained by adding a three-stage differential amplifier to a conventional feedback amplifier monolithically integrated with a surface-illuminated p-i-n photodiode. The circuit configuration gave a preamplifier a transimpedance of 60 dBΩ. The receiver OEIC achieved error-free operation at 10 Gbit/s without a postamplifier even with the optical input as low as -10.3 dBm because of its large O/E conversion factor of 890 V/W. A two-channel receiver OEIC array for use in a 10-Gbit/s parallel photoreceiver module based on a PLC platform was made by monolithically integrating multimode WGPD's with HEMT preamplifiers. The side-illuminated structure of the WGPD is suitable for integration with other waveguide-type optical devices. The receiver OEIC arrays were fabricated on a 2-inch wafer with achieving excellent uniformity and a yield over 90%: average transimpedance and average 3-dB-down bandwidth were 43.8 dBΩ and 8.0 GHz. The two channels in the receiver OEIC array also showed sensitivities of -16.1 dBm and -15.3 dBm at 10 Gbit/s. The two-channel photoreceiver module was constructed by assembling the OEIC array on a PLC platform. The frequency response of the module was almost the same as that of the OEIC chip and the crosstalk between channels in the module was better than -27 dB in the frequency range below 6 GHz. These results demonstrate the feasibility of using our receiver OEIC's in various types of optical receiver systems.

Waveguide photodiodes (WGPDs) are key devices for high-speed optical receivers in trunk lines because of their potential ability to provide both high efficiency and a high-speed response. We have designed a waveguide photodiode for 40-Gb/s-range optical receivers. The optical coupling characteristics were simulated in detail to optimize the waveguide structure, and the electrodes of the photodiode were designed to form a coplanar transmission line to match the system impedance, which minimized frequency-response degradation. A highly beryllium-doped, low-temperature-grown InGaAs contact layer grown by gas source molecular beam epitaxy was used to reduce the series resistance, and approximately 40% reduction of series resistance was achieved. The fabricated device exhibited both a very high external quantum efficiency of 81% for 1.55-µm light and a sufficient bandwidth of more than 40 GHz. Though we used a simple conventional fabrication process, excellent characteristics were achieved due to the optimized optical design and well suppressed parasitic parameters.

Waveguide photodiodes (WGPDs) are key devices for high-speed optical receivers in trunk lines because of their potential ability to provide both high efficiency and a high-speed response. We have designed a waveguide photodiode for 40-Gb/s-range optical receivers. The optical coupling characteristics were simulated in detail to optimize the waveguide structure, and the electrodes of the photodiode were designed to form a coplanar transmission line to match the system impedance, which minimized frequency-response degradation. A highly beryllium-doped, low-temperature-grown InGaAs contact layer grown by gas source molecular beam epitaxy was used to reduce the series resistance, and approximately 40% reduction of series resistance was achieved. The fabricated device exhibited both a very high external quantum efficiency of 81% for 1.55-µm light and a sufficient bandwidth of more than 40 GHz. Though we used a simple conventional fabrication process, excellent characteristics were achieved due to the optimized optical design and well suppressed parasitic parameters.

This paper describes a 2.5-Gb/s optical receiver and transmitter chipset consisting of a preamplifier, a main amplifier, a clock and data recovery (CDR) circuit, and a laser-diode (LD) driver. Low-voltage and adjustment-free circuit techniques are introduced in order to achieve low cost and low power circuits. Circuit adjustments are eliminated by using a multi-stage automatic offset canceling technique in the main amplifier, and by using a PLL structure with a sample-and-hold technique in the CDR circuit. For power reduction, ICs are operated at a power supply voltage of -3 V. Fabricating the ICs by a 0.5-µm Si bipolar process makes it possible to achieve 2.5-Gb/s receiver and transmitter operation with a total power dissipation of 1.04 W. Especially significant is that the receiver ICs need no external devices and adjustments.

An optical receiver with a saturated electrical amplifier is studied for signal light that is distorted due to the use of a gain-saturated semiconductor optical amplifier or homowavelength crosstalk light. It is shown that less penalty is induced in a receiver with a DC-coupled saturated amplifier than in one with a linear amplifier, in a practical situation where the decision threshold is fixed at a value optimized for a back-to-back signal. The result suggests that a receiver with a saturated amplifier or a limitter is preferable to an automatic gain control circuit for detecting distorted signal lights.

Optical frontend and distributed amplifier IC modules, both containing GaAs heterojunction-bipolar-transistors (HBT), have been developed for 40 Gb/s optical receiver. To achieve high-speed operations, the elements in the modules including the IC and signal lines, were designed to achieve a wider bandwidth with lower electrical reflection. The influence of a bonding-wire inductance was taken into particular account in optimizing the parameters of the ICs. The optical frontend, consisting of a waveguide pin-photodiode and an HBT preamplifier IC, exhibits a transimpedance gain of 43 dBΩ and a bandwidth of 31 GHz. The distributed amplifier IC module achieves a gain of 9 dB and a bandwidth of 39 GHz. A 40-Gb/s optical receiver constructed with these modules exhibited a high receiver sensitivity of -28. 2 dBm for a 40-Gb/s optical return-to-zero signal.

An optical receiver for hybrid SCM video distribution systems that distribute AM, QAM (quadrature amplitude modulation) and FM TV signals simultaneously is investigated. We propose a novel receiver configuration called the Frequency Division type Receiver (FDR) with consists of a photo detector, filter, and multiple preamplifiers. The receiver is compared with existing receivers in terms of optical sensitivity, distortion characteristics, and configuration simplicity. We clarify that the newly developed FDR type receiver is most suitable for hybrid SCM video distribution systems.

We have successfully developed an optical receiver and a laser driver circuit which were implemented with 0.35 µm GaAs JFETs (junction Field Effect Transistors). The 0.35 µm GaAs. JFET had the typical transconductance of 480 mS/mm with small drain conductance. An interdigit MSM (Metal Semiconductor Metal) -type photodetector and the JFETs were monolithically integrated on a GaAs substrate for the optical receiver. The fabricated optical receiver demonstrated Gb/s operation with a very low power consumption of 8.2 mW. The laser driver circuit operated at up to 4.0 Gb/s.