Congestion Control Scheme of TCP/IP protocol suite is established by Transmission Control Protocol (TCP). Using the self-clocking scheme, TCP is able to maintain a quick optimum connection status for the network path, unless it is given an excessive load to carry to the network. However, in wide area networks, there are some obstructive factors for the self-clocking scheme of TCP. In this paper, we describe the obstructive factors for the self-clocking scheme. We propose a new congestion control scheme using a packet pair scheme and a traffic-shaping scheme. In combining these schemes with TCP, new TCP options and a modification for TCP congestion control algorithms are added. Using our scheme, TCP is able to maintain smooth self-clocking. We implemented this scheme on a network simulator for evaluation. Compared with normal TCP, this scheme was demonstrated to be over 20% more efficient in symmetric communication and over 40% more efficient in asymmetric communication.

In this paper we propose a method to aid a visually impaired person in the operation of a computer running a graphical user interface (GUI). It is based on image processing techniques, using images taken by a color camera placed over a Braille display. The shape of the user's hand is extracted from the image by analyzing the hue and saturation histograms. The orientation of the hand, given by an angle θ with the vertical axis, is calculated based on central moments. The image of the hand is then rotated to a normalized position. The number of pixels in each column of the normalized image is counted, and the result is put in a histogram. By analyzing the coefficient of asymmetry of this histogram, it can be determined whether the thumb is positioned along the pointing finger, or whether it is far from the other fingers. These two positions define two states that correspond to a mouse button up or down. In this way, by rotating the hand and moving the thumb, we can emulate the acts of moving a scroll bar and depressing a mouse button, respectively. These operations can be used to perform tasks in a GUI, such as cut-and-paste, for example. Experimental results show that this method is fast and efficient for the proposed application.

Testing for delay faults is very important in the verification of the timing behavior of digital circuits. When a circuit which is unable to operate at the desired clock speed is identified, it is necessary to locate the delay fault(s) affecting the circuit in order to remedy the situation. In this paper, we present a path-tracing method of multiple gate delay fault diagnosis in combinational circuits. We first present the basic rules for deducing suspected faults based on the multiple gate delay fault assumption. Next, in order to improve diagnostic resolution, we introduce rules for deducing non-existent faults based on the fault-free responses at the primary outputs. Using these rules, we present the detailed method for diagnosing multiple delay faults based on paths sensitized by test-pairs generated for marginal delays and gate delay faults [7]. Finally, we present results obtained from experiments on the ISCAS '85 benchmark circuits. The experimental results show the effectiveness of our method.

A new multiple-valued current-mode (MVCM) integrated circuit using a switched current-source control technique is proposed for a 1.5 V-supply high-speed arithmetic circuit with low-power dissipation. The use of a differential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In the proposed DLC using a switched current control technique, the static power dissipation can be greatly reduced because current sources in non-active circuit blocks are turned off. Since the gate of each current source is directly controlled by using a multiphase clock whose technique has been already used in dynamic circuit design, no additional transistors are required for currentsource control. As a typical example of arithmetic circuits, a new 1.5 V-supply 5454-bit multiplier based on a 0.8µm standard CMOS technology is also designed. Its performance is about 1.3 times faster than that of a binary fastest multiplier under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the proposed MVCM integrated circuit.

A new linearization technique of a transconductor is presented. The linearization is realized by using a differential current amplifier with an emitter-coupled pair. A specific value of the linearization parameter gives a maximally flat or an equiripple characteristic. Deviations from the theoretical characteristic can be adjusted by tuning the tail current of the emitter-coupled pair. The proposed technique is demonstrated by PSPICE simulation.

This paper presents a method of multiple fault diagnosis in sequential circuits by input-sequence pairs having sensitizing input pairs. We, first, introduce an input-sequence pair having sensitizing input pairs to diagnose multiple faults in a sequential circuit represented by a combinational array model. We call such input-sequence pair the sensitizing sequence pair in this paper. Next, we describe a diagnostic method for multiple faults in sequential circuits by the sensitizing sequence pair. From a relation between a sensitizing path generated by a sensitizing sequence pair and a subcircuit, the proposed method deduces the suspected faults for the subcircuits, one by one, based on the responses observed at primary outputs without probing any internal line. Experimental results show that our diagnostic method identifies fault locations within small numbers of suspected faults.

Checkers, self-testers, and self-correctors for a function f are powerful tools in designing programs that compute f. However, the relationships among them have not been known well. In this paper, we first show that (1) if oneway permutations exist, then there exists a language L that has a checker but does not have a self-corrector. We then introduce a novel notion of "self-improvers" that trans form a faulty program into a less faulty program, and show that (2) if a function f has a self-tester/corrector pair, then f has a self-improver. As the applications of self-improvers, we finally show that (3) if a function f has a self-tester/corrector pair, then f has a flexible self-tester and (4) if a function f has a self-tester/corrector pair, then f has self-improver that transforms a faulty program into an alomost correct program.

In this paper, we propose an approach for railway scheduling based on iterative repair, a technique that starts with a complete but possibly flawed schedule and searches through the space of possible repairs. The search is guided by an earliest-conflict-first heuristic that attempts to repair the earliest constraint violation while minimizing the value of objective function. Since cycles may exist among a sequence of repairs during the repair process, a cycle detection and resolution scheme is proposed to prevent infinite loops. Experimental results show that the efficiency of the repair algorithm improves significantly when cycle detection is incorporated.

A radial line slot antenna (RLSA) is a high efficiency and high gain planar antenna. The efficiency of RLSA becomes lower as the aperture size reduces due to rotational asymmetry of the illumination. A concentric array RLSA (CA-RLSA) was proposed to overcome this difficulty. It adopted three new techniques; (1) not spirally but concentrically arrayed slots, (2) a rotating mode feed circuit, (3) matching slot pairs eliminating termination loss. This paper proposes the basic slot design for (1) and (2) of CA-RLSA. Excellent characteristics of very small CA-RLSAs based upon this design are confirmed by measurements.

This paper discusses the reliability of the Modified EBU method compared with the EBU and DSCQS methods where the small and different levels of impairments exist in the coded HDTV sequences. The subjective evaluation tests are carried out in the full and limited impairment ranges. And it is shown that the Modified EBU method is most reliable for both ranges.

This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate a test generation procedure previously proposed and reduce the number of test vectors generated, while higher fault coverage is derived. The first technique proposed in this paper, which is applied at the first phase of test generation, is rules of ordering vector pairs to be analyzed, to derive high fault coverage without repeating the analysis for the same vector pairs. The second one is to generate new vector pairs for undetected faults, instead of random vector pairs. Both techniques are based on the idea that faults close to primary inputs should be detected earlier than close to primary outputs. The third technique proposed here is how to construct vector pairs from one input vector in order to accelerate test generation especially for circuits with many primary inputs and scan flip-flops. Experimental results for bench-mark circuits show the effectiveness of the techniques.

An efficient algorithm is given for finding all solutions of piecewise-linear resistive circuits containing nonseparable transistor models such as the Gummel-Poon model or the Shichman-Hodges model. The proposed algorithm is simple and can be easily programmed using recursive functions.

Damgrd defined the notion of a collision intractable hash functions and showed that there exists a collection of collision intractable hash functions if there exists a collection of claw-free permutation pairs. For a long time, the necessary and sufficient condition for the existence of a collection of collision intractable hash functions has not been known, however, very recently Russell finally showed that there exists a collection of collision intractable hash functions iff there exists a collection of claw-free pseudo-permutation pairs. In this paper, we show an alternative necessary and sufficient condition for the existence of a collection of collision intractable hash functions, i.e., there exists a collection of collision intractable hash functions iff there exists a collection of distinction intractable pseudo-permutations.

Many methods, based on the concept of key-lock-pair have been proposed for access control in computer protection systems. However, the proposed methods still either lack of dynamic ability or need quite a lot of computation in performing requests of deleting users/files, inserting users/files, or updating access rights of users to files. In this paper we propose a two-key-lock-pair access control method that is based on the unique factorization theorem and a time stamp mechanism. Our method is dynamic and needs a minimum amount of computation in the sense that it only updates at most one key/lock for each access request, which has not been achieved before.

Kumar and Billinton have presented a new technique for obtaining the steady-state probabilities from a flow graph based on Markov model. By examining the graph and choosing suitable input and output nodes, the steady-state probabilities can be obtained directly by using the flow graph. In this paper this graphical technique is applied for a k-out-of-n: G repairable system. Consequently a new derivation way of the formulae for the steady-state availability and MTBF is obtained.

This paper proposes a repairable and diagnosable k-valued cellular array. We assume a single fault, i.e., either stuck-at-O fault or stuck-at-(k1) fault of switches occurs in the array. By building in a duplicate column iteratively, when a stuck-at-(k1) fault occurs in the array, the fault never influences the output of the array. That is, we can construct a fault-tolerant array for the stuck-at-(k1) fault. While, for the stuck-at-O fault, the diagnosing method is simple and easy because we don't have to diagnose the stuck-at-(k1) fault. Moreover, our array can be repaired easily for the fault. The comparison with other rectangular arrays shows that our array has advantages for the number of cells and the cost of the fault diagnosis.

Resonant slots are widely used for conventional slotted waveguide array. Reflection from each slot causes a standing wave in the waveguide and beam tilting technique is essential to suppress the reflection at the antenna input port. But the slot reflection narrows the overall frequency bandwidth and the design taking it into account is complicated. This paper proposes a reflection cancelling slot pair as an array element, which consists of two slots spaced by 1/4λg. Round trip path-length difference between them is 1/2λg and reflection waves from a pair disappear and traveling-wave excitation in the waveguide is realized. The full wave analysis reveals that mutual coupling between paired slots is large and seriously reduces the radiation from a pair. Offset arrangement of slots in a pair is recommended to decrease the mutual coupling and to realize strong coupling. In practical array design, the mutual couplings from other pairs were simulated by imposing periodic boundary conditions above the aperture. To clarify the advantages of the slot pair over a conventional resonant slot, the predicted characteristics are compared. Reflection characteristics of the array using the slot pair is excellent and a boresite beam array can be realized. In addition, a slot pair can realize stronger coupling than the conventional resonant slot, while the bandwidth of the former in terms of the aperture field phase illumination is narrower than that of the latter. These suggests that the slot pair array is much more suitable for a small array than conventional one. Finally, the predicted characteristics are confirmed by experiments.

Mean Time Between Failures (MTBF) is an important measure of practical repairable systems, but it has not been obtained for a repairable linear consecutive-k-out-of-n: F system. We first present a general formula for the (steady-state) availability of a repairable linear consecutive-k-out-of-n: F system with nonidentical components by employing the cut set approach or a topological availability method. Second, we present a general formula for frequency of system failures of a repairable linear consecutive-k-out-of-n: F system with nonidentical components. Then the MTBF for the repairable linear consecutive-k-out-of-n: F system is shown by using the frequency of system failure and availability. Lastly, we derive some figures which show the relationship between the MTBF and repair rate µorρ(=λ/µ) in the repairable linear consecutive-k-out-of-n: F system. The figures can be easily used and are useful for reliability design.

Finding DC solutions of nonlinear networks is one of the most difficult tasks in circuit simulation, and many circuit designers experience difficulties in finding DC solutions using Newton's method. Piecewise-linear analysis has been studied to overcome this difficulty. However, efficient piecewiselinear algorithms have not been proposed for nonlinear resistive networks containing the Gummel-Poon models or the Shichman-Hodges models. In this paper, a new piecewise-linear algorithm is presented for solving nonlinear resistive networks containing these sophisticated transistor models. The basic idea of the algorithm is to exploit the special structure of the nonlinear network equations, namely, the pairwise-separability. The proposed algorithm is globally convergent and much more efficient than the conventional simplical-type piecewise-linear algorithms.

To make a fast Bi-CMOS SRAM yield high without speed degradation, three defect-repair methods, the address comparison method, the fuse decoder method and the distributed fuse method, were considered in detail and their advantages and disadvantages were made clear. The distributed fuse method is demonstrated to be further improved by a built-in fuse word driver and a built-in fuse column selector, and fuse analog switches. This enhanced distributed fuse scheme was examined in a fast Bi-CMOS SRAM. A maximun access time of 14 ns and a chip size of 8.8 mm17.4 mm are expected for a 4 Mb Bi-CMOS SRAM in the future.