There are two approaches to implementing the international standard video coding algorithms such as H.261 and MPEG: a programmable DSP approach and a building block approach. The advantages and disadvantages of each are discussed here in detail, and the video coding algorithms and required throughput are also summarized. For more complex standard such as MPEG-, VLSI architecuture became more sophisticated. The DSP approach incorporates special processing engines and the building block approach integrates general-purpose microprocessors. Both approaches are capable of MPEG- NTSC coding in a single chip. Reduction of power consumption is a key issue for video LSIs. Architectures and circuits that reduce the supply voltage while maintaining throughput are summarized. A 0.25-µm, 3-GOPS, 0.5-W, SIMD-VSP for portable MPEG- systems could be made by using architecture-driven voltage scaling as well as feature-size scaling and SOI devices.

This paper proposes a new environment for high-level VLSI design specification validation using "Algorithmic Debugging" and evaluates its benefits on three significant examples (a protocol processor, an 8-bit CPU, and a Prolog processor). A design is specified at a high-level using the structured analysis (SA) method, which is useful for analyzing and understanding the functionality to be realized. The specification written in SA is transformed into a logic programming language and is simulated in it. The errors (which terminate with an incorrect output in the simulation) included in the three large examples are efficiently located by answering junt a few queries from the algorithmic debugger. The number of interactions between the designer and the debugger is reduced by a factor of ten to a hundred compared to conventional simulation based validation methodologies. The correct SA specification can be automatically translated into a Register Transfer Level (RTL) specification suitable for logic synthesis. In this environment, a designer is freed from the tedious task of debugging a RTL specification, and can concentrate on the design itself. This environment promises to be an important step towards efficient high-level VLSI design specification validation.

We present a new multi-layer over-the-cell channel router for standard cell layout design using simulated annealing. This new approach, STANZA-M consists of two key features. The first key feature of our router is a new scheme for simulated annealing in which we use a cost function to evaluate both the total net-length and the channel heights, and an effective simulated annealing process by a limited range to obtain an optimal chnnel wiring in practical time. The second feature of our router is a basic layer assignment procedure in which we assign all horizontal wiring inside a channel to feasible layers by considering the height of channel including cell region with a one dimensional channel compaction process. We implemented our three-layer cannel router in C language on a Solbourne Series 5 Work Station (22 MIPS). Experimental results for benchmarks such as Deutsch's Difficult Example and MCNC's PRIMARY1 channel routing problems indicate that STANZA-M can achieve superior results compared to the conventional routers, and the process times are very fast despite the use of simulated annealing.

Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.

This paper proposes a new signaling technique which employs multilevel block codes in conjunction with phase/frequency modulation. The proposed scheme exhibits an increased minimum squared Euclidean distances (MSEDs) and outperforms other conventional schemes in terms of asymptotic coding gain and decoding complexity. The proposed scheme is also considered for non-constant amplitudes, which turned out to show even better performances at small modulation indices in some cases. Examples are given to demonstrate how to optimize the signal set for a given block code to maximize the coding gain.

This paper proposes a methodology for fine evaluation of the uncertain behaviors of systems affected by any fluctuation of internal structures and internal parameters, by the use of a new concept on the fuzzy mapping. For a uniformly convex real Banach space X and Y, a fuzzy mapping G is introduced as the operator by which we can define a bounded closed compact fuzzy set G(x,y) for any (x,y)∈X×Y. An original system is represented by a completely continuous operator f defined on X, for instance, in a form xλ(f(x)) by a continuous operator λ: YX. The nondeterministic fluctuations induced into the original system are represented by a generalized form of the fuzzy mapping equation xGβ (x,f(x)) {ζX|µG(x,f(x))(ζ)β}, in order to give a fine evaluation of the solutions with respect to an arbitrarily–specified β–level. By establishing a useful fixed point theorem, the existence and evaluation problems of the "β–level-likely" solutions are discussed for this fuzzy mapping equaion. The theory developed here for the fluctuation problems is applied to the fine estimation of not only the uncertain behaviors of system–fluctuations but also the validity of system–models and -simulations with uncertain properties.

The concept of flexible system is long being used by many researchers, aiming to solve some particular problem of adaptation. The problem is viewed differently in different situations. In this paper, we first give a set of definitions and specifications to generalize this concept applicable to any system and in particular to communication networks. Through these definitions we will formalize, what are the conditions a system should satisfy to be called as a Flexible Communication System. The rest of the paper we formalize the concepts of flexible information network, and propose an agent oriented architecture that can realize it.

Along with the improvement of micro processors and local area networks, a distributed system becomes useful to realize a telecommunication system. It has potential advantage to achieve both high performance and high reliability. However, the design of a distributed system tends to be more complicated compared to a conventional centralized system. For the purpose of the standardization of distributed processing, ISO and ITU-T study the Open Distributed Processing (ODP) and are currently standardizing the Basic Reference Model of ODP (RM-ODP). To avoid dealing with the complexity of distributed systems, RM-ODP defines five viewpoints. The viewpoint approach of RM-ODP is proposed as a framework for the design of a distributed system. Although some previous works give the design methods of distributed systems based on the ODP viewpoint approach, the detailed design method has not been fully specified or all of the five viewpoints are not taken into account. In this paper, we describe a detailed design method for a distributed telecommunication system based on the ODP viewpoint approach. The method applies the five viewpoints to the three phases of design of a distributed system, that is, requirement analysis, functional design and detailed design phase. It clarifies what specifications for the target system should be made from the individual viewpoints and how the specifications are related each other. It also takes account of the platform which provides the distribution support, and gives the design method for both the platform and the application specific functions on the platform. The design method is examined by applying it to the design of a distributed MHS system supporting X.400 series protocols. In this example, the remote procedure call based on the client-server model is selected as the base of the platform. The result shows that our method is useful to simplify the complexity of the design for a distributed telecommunication system.

The design theory was revealed by theoretical analysis of the measuring apparatus, and was confirmed experimentally. Higher quality tags having new circuit disigns were proposed by the revealed theory. The measuring apparatus equivalent to the security system was produced to estimate the properties of the LC resonant circuit security tags quantitatively.

By applying Wigner distribution, which has high time resolution and high random noise reducing capability, to the acoustic bio–signals, the possibility of early diagnosis in both intracranial vascular deformation and prosthetic cardiac valve malfunction increased. Especially in latter case, 1st–order local moment of the distribution showed its effectiveness.

By addressing design requirements for multicast ATM switching, this paper attempts to provide an integrated view of modular and expandable switch architectures suitable for both unicast and multicast switching for future B-ISDNs. Several large and modular multicast ATM switching architectures are discussed, each of which handles different traffic situations. These architectures consist of multiple shared-buffer copy network modules of adequate size suitable for fabrication on a single chip, and small output memory switch modules. A new modular link-grouped multistage interconnection network is proposed for interconnecting copy network modules and memory switch modules, so that future large multicast ATM switching networks can be built in a modular fashion. The described modular architectures can significantly facilitate signal synchronization in large-scale switching networks.

In this paper, the power dissipation issue is considered in the gate sizing procedure. In order to observe the tradeoff among area, delar and power dissipation in a circuit, gate sizing algorithms which can minimize power under delay constraints or minimize area under power and delay constraints are formulated. Experiments are performed to investigate the properties of area–power–delay tradeoff in the gate sizing procedure.

This paper describes a procedural detailed compaction method for the symbolic layout design of CMOS leaf cells and its algorithmic aspects. Simple symbolic representations that are loosely designed by users in advance are automatically converted into densely compacted physical patterns in two phases: symbolic–to–pattern conversion and segment–based detailed compaction. Both phases are executed using user-defined procedures and a specified set of design rules. The detailed compaction utilizes a segment–based constraint graph generated by an extended plane sweep method where various kinds of design rules can be applied. Since various kinds of basic operations can be applied to the individual segments of patterns in the procedures, the detailed procedure for processing can be described in accordance with fabrication process technologies and the corresponding sets of design rules. This combined stepwise procedure provides a highly flexible framework for the symbolic layout of CMOS leaf cells. The proposed approach was implemented in a symbolic layout system called CAMEL. To date, more than 300 kinds of symbolic representations of CMOS leaf cells have been designed and are stored in the database. Using several different sets of design rules, symbolic representations have been automatically converted into compacted patterns without design rule violations. The areas of those generated patterns were averaged at 98% of the manually designed patterns. Even in the worst case, the increases in area were less than about 10% of the manually designed ones. Furthermore, since processing times are much shorter than manual design periods, for example, 300 kinds of symbolic representations can be converted to corresponding physical patterns in only a day. It is evident, through these practical design experiences with CAMEL, that our approach is more flexible and process–tolerant than conventional ones.

In the design of 3-D filter detecting Linear Trajectory Signal (LTS), there may be paid little attention to the noise rejective characteristics. In this paper, we treat the noise rejection ability of the filter detecting LTS having margins both in its velocity and direction.

This paper describes a newly developed 22 liquid crystal optical switch for 1.3µm single-mode fiber use. This switch state can be freely set at either the cross or the bar state. The measured performance of two prototype 22 liquid crystal optical switches is given. Tests confirm that the 3 values are a maximum insertion loss of 1.5dB, a crosstalk attenuation of more than 26.1dB, and a return loss of more than 28.9dB. Requirements for optical switches for fault isolation are theoretically clarified from a LAN system view point.

This paper describes a preconstrained compaction method and its application to the direct design-rule conversion of CMOS layouts. This approach can convert already designed physical patterns into compacted layouts that satisfy user-specified design rules. Furthermore, preconstrained compaction can eliminate unnecessarily extended diffusion areas and polysilicon wires which tend to be created with conventional longest path based compactions. Preconstrained compaction can be constructed by combining a longest path algorithm with forward and backward slack processes and a preconstraint generation process. This contrasts with previously proposed approaches based on longest path algorithms followed by iterative improvement processes, which include applications of linear programming. The layout styles in those approaches are usually limited to a model where fixed-shaped rectilinear blocks are moved so as to minimize the total length of rectilinear interconnections among the blocks. However, preconstrained compaction can be applied to reshaping polygonal patterns such as diffusion and channel areas. Thus, this compaction method makes it possible to reuse CMOS leaf and macro cell layouts even if design rules change. The proposed preconstrained compaction approach has been applied to direct design-rule conversion from 0.8-µm to 0.5-µm rules of CMOS layouts containing from several to 10,195 transistors. Experimental results demonstrate that a 10.6% reduction in diffusion areas can be achieved without unnecessary extensions of polysilicon wires with a 39% increase in processing times compared with conventional approaches.

The relation between computing part of the FFT spectrum and the so-called generalized FFT (GFFT) is clarified, leading to a new algorithm for performing partial FFTs. The method can be applied when only part of the output is required or when the input data sequence contains many zeros. Such cases arize for example in decimation and interpolation and also in computing linear convolutions. The technique consists of decomposing the DFT into several generalized DFTs. Efficient algorithms for these generalized DFTs exist. The computational complexity of the new approach is roughly equal to the complexity of previous techniques, but the structure is superior, because only one type of butterfly is used and a few lines of code are sufficient. The theoretical properties of the GDFT are given. The case of multidimensional signals, defined on arbitrary sampling lattices is also considered.

A method for evaluating the degradation of subband adaptive digital filters (ADF) is presented. The performance of a simple ADF that uses critical sampling is mainly influenced by the subband filter bank's characteristics and the finite precision arithmetic operations used. This paper considers a two-channel mirror filter bank and a normalized least mean square algorithm with floating point arithmetic. The theoretical ERLE (Echo Return Loss Enhancement) and the theoretical relationships between the output error of the ADF and the circuit parameters considering finite precision A/D conversion and finite word length effects in floating point arithmetic operation are obtained using an equivalent noise model. Simulation results are found to be in good agreement to analytical values; the difference is only 3 to 5 dB.

Kalman filter is an essential tool in signal processing, modern control and communications. The filter estimates the states of a given system from noisy measurements, using a mean-square error criterion. Although Kalman filter has been shown to be very versatile, it has always been computationally intensive since a great number of matrix computations must be performed at each iteration. Thus the exploitation of this technique in broadband real time applications is restricted. The solution to these limitations appears to be in VLSI (very large scale integration) architectures for the parallel processing of data, in the form of systolic architectures. Systolic arrays are networks of simple processing cells connected only to their nearest neighbors. Each cell consists of some simple logic and has a small amount of local memory. Overall data flows through the array are synchronously controlled by a single main clock pulse. In parallel with the development of Kalman filter, the square root covariance and the square root information methods have been studied in the past. These square root methods are reported to be more accurate, stable and efficient than the original algorithm presented by Kalman. However it is known that standard SRIF is less efficient than the other algorithms, simply because standard SRIF has additional matrix inversion computation and matrix multiplication which are difficult to implement in terms of speed and accuracy. To solve this problem, we use the modified Faddeeva algorithm in computing matrix inversion and matrix multiplication. The proposed algorithm avoids the direct matrix inversion computation and matrix multiplication, and performs these matrix manipulations by Gauss elimination. To evaluate the proposed method, we constructed an efficient systolic architecture for standard SRIF using the COMPASS design tools. Actual VLSI design and its simulation are done on the circuits of four type processors that perform Gauss elimination and the modified Givens rotation.

A new steepest descent linear adaptive algorithm, called the proportion-sign algorithm (PSA), is introduced and its performance analysis is presented when the signals are from zero-mean jointly stationary Gaussian processes. The PSA improves the convergence speed over the least mean square (LMS) algorithm without overly degrading the steady-state error performance and has the robustness to impulsive interference occurring in the desired response by adding a minimal amount of computational complexity. Computer simulations are presented that show these advantages of the PSA over the LMS algorithm and demonstrate a close match between theoretical and empirical results to verify our analysis.