This paper describes an exact symbolic formulation of resource-constrained scheduling which allows speculative operation execution in arbitrary forward-branching control/data paths. The technique provides a closed-form solution set in which all satisfying schedules are encapsulated in a compressed OBDD-based representation. An iterative construction method is presented along with benchmark results. The experiments demonstrate the ability of the proposed technique to efficiently extract parallelism not explicitly specified in the input description.

We developed a new test-synthesis that operates method based on data transfer analysis at the language level. Using this method, an efficient scan path is inserted to generate test data for the sequential circuit by using only a test generation tool for the combinatorial circuit. We have applied this method successfully to the behavior, logic, and test design of a 32-bit, RISC-type processor. The size of the synthesized circuit without test synthesis is 23,407 gates; the size with test synthesis is 24,811 gates. This is an increase of only a little over 6%.

In this paper, we propose an efficient method (called DIRIC algorithm) to allocate carrier frequencies so as to minimize intermodulation products in two-level SCPC systems in which Hub station and many Remote stations communicate each other through satellite transponder. We also present a very efficient method to evaluate intermodulation products with substantially reduced CPU time in two-level SCPC systems. We compare and analyze the performance of several frequency allocation methods to extend DELINS-INSDEL algorithm (which is proposed by Okinaka) to two-level SCPC systems. When the proposed algorithm is applied to systems with modulated carrier, it is verified that this algorithm has the same efficiency as the unmodulated carrier. It is also shown heuristically that certain initial assignment algorithms perform better than random assignment.

A key element in the CDMA transmission is DS spreading. Spreading in a DS/SSMA system are provided in two categories-synchronization and data. For synchronization sequences, good auto-correlation and cross-correlation properties are required in order to guarantee fast acquistion with a minimum false alarm probability. On the other hand, the auto-correlation property may not be so important in data spreading since synchronization is obtained by synchronization spreading. In this paper we provide a set of synchronization sequences and a set of data sequences--each a set of binary N-tuples--that have the necessary correlation constraints.

In this paper we propose a co-design method for control systems using combination of models. By co-design," we mean a cooperative design method in which the behavior of the entire system is simulated as a single model while parameters of the system are being optimized. Our co-design method enables the various subsystems in the system, which have been designed independently as tasks assigned to different designers in the traditional design method, to be designed simultaneously in a unified cooperative way from the system-wide perspective of a system designer. Our proposed method combines models of controlling and controlled subsystems into a single model for the behavior of the entire control system. After the optimum control conditions are determined through simulation of the combined models, based on the corresponding algorithms and parameters, ASIC design proceeds quickly with accurate verification using iterative replacements of the behavior model by the electronic circuit model. To evaluate the proposed method, we implemented a design environment. We then applied our method to the design of ASICs in three test cases (in a control system and in audio-visual systems) to investigate its effectiveness. This paper introduces the concepts of the proposed co-design method, the design environment and the experimental results, and points out the new issues for system design.

We give a tutorial on high-level synthesis of VLSI. The evolution of digital system synthesis techniques and the need for higher level design automation tools are first discussed. We then point out essential issues to the successful development and acceptance by the designers of a high-level synthesis system. Techniques that have been proposed for various subtasks of high-level synthesis are surveyed. Possible applications of the high level synthesis in area other than chip design are forecast. Finally, we point out several directions for possible future research.

This paper describes an efficient slew rate enhancement technique especially suitable for an operational amplifier used in an LCD driver IC. This technique employs an input-dependent biasing without directly monitoring an input; instead, monitoring an output of the first stage of the amplifier. This enhancement technique is easily applied to a conventional two-stage operational amplifier and requires only 8 additional transistors to increase slew rates for both rising and falling edges. The bias currents of the first and the second stages are simultaneously controlled by this biasing. Experimental operational amplifiers with and without this enhancement have been fabricated to demonstrate the improvement of slew rate. Slew rates of 12.5V/µsec for the rising edge and 50V/µsec for the falling edge with a 100 pF load capacitance have been achieved by this technique, compared with slew rates of 0.3V/µsec for the rising edge and 5V/µsec for the falling edge in the conventional amplifier.

This paper proposes a new approach for the development of a module generator that can parameterize both the size and the structure of layout. The proposed method acquires a design procedure from the design process of a designer, and reuses it to synthesize new layouts with different input parameters that affect the size or the structure of layout. In this method, a designer creates a module layout on a layout editor instead of writing a program. From his design process, a procedure to synthesize the layout is automatically derived. Then, it is generalized so that it could be valid under different values of input parameters. The generalized procedure is independent of design rules, and is capable of synthesizing error-free module layouts of different size and structure. Also, the procedure includes designer's requirements on how the layout should be designed. The experimental results of applying the approach for developing generators of analog device components show effectiveness of our approach.

An efficient algorithm is given for finding all solutions of piecewise-linear resistive circuits containing nonseparable transistor models such as the Gummel-Poon model or the Shichman-Hodges model. The proposed algorithm is simple and can be easily programmed using recursive functions.

We present a design chart and a manufacturing process for mm-wave absorber consisting of two spacers (poly-carbonate) and two-resistive sheets (polyethylene terephthalate deposited with Indium Tin Oxide). The conventional design chart gives us necessary information to make a desirable absorber. Based on the design chart, a multi-layered type absorber was manufactured and it is concluded that a significant absorption level (-20dB) is attained at a wide-frequency range of 46-66GHz.

On mutually coupling lines, the transmission signal is dispersively propagated by crosstalk coupling between lines and shows complex propagation characteristics caused by reciprocal reflections. Usually, the differential equation and the integral equation have been applied to analyze the solutions of transmission lines. In this paper, we propose a different analytical method of the propagation characteristics of signal and crosstalk noise. By setting up crosstalk coupling line as a sectionally divided digital transmission network and by using the signal flow graph and the difference equation, the propagation characteristics in the frequency domain, the space domain and the time domain on mutually coupling lines can be obtained. To verify the validity of this method and analyze the complex propagation problems, we first study the crosstalk characteristics of a twisted pair cable via the third circuit by unidirectional coupling. Subsequently we will analyze the coupling theory of bidirectional coupling lines.

This paper proposes a large capacity high-speed file memory system implemented with wafer scale RAM which adopts a novel defect-tolerant technique. Based on set-associative mapping, the defective memory blocks on the wafer are repaired by switching with the spare memory blocks. In order to repair the clustered defective blocks, these are permuted logically with other blocks by adding some constant value to the input block addresses. The defective blocks remaining even after applying the above two methods are repaired by using error control codes which correct soft errors induced by alpha particles in an on-line operation as well as hard errors induced by the remaining defective blocks. By using the proposed technique, this paper demonstrates a large capacity high-speed WSI file memory system implemented with high fabrication yield and low redundancy rate.

In this paper, a design of TCM signals for Middleton's class-A impulsive noise environment is investigated. The error event characteristics under the impulsive noise is investigated, and it is shown that the length of the signal sequence is more important than Euclidean distance between the signal sequences. Following this fact, we introduce the shortest error event path length as a measure of the signal design. In order to make this value large, increasing of states of convolutional codes is employed, and the performance improvement achieved by this method is evaluated. Numerical results show the great improvement of the error performance and conclude that the shortest error event path length is a good measure in the design of TCM signals under impulsive noise environment. Moreover, the capacity of class-A impulsive noise channel is evaluated, and the required signal sets expansion rates to obtain the achievable coding gain is discussed.

This paper discusses sign word segmentation methods and extraction of motion features for sign language recognition. Because Japanese sign language grammar has not yet been systematized and because sign language does not have prepositions, it is more difficult to use grammar and meaning information in sign language recognition than in speech recognition. Segmentation significantly improves recognition efficiency, so we propose a method of dividing sign language based on rests and on the envelope and minimum of motion speed. The sign unit corresponding to a sign word is detected based on the divided position using such features as the change of hand shape. Experiments confirmed the validity of word segmentation of sign language based on the temporal structure of motion.

An efficient algorithm is presented for finding all solutions of piecewise-linear resistive circuits containing sophisticated transistor models such as the Gummel-Poon model or the Shichman-Hodges model. When a circuit contains these nonseparable models, the hybrid equation describing the circuit takes a special structure termed pairwise-separability (or tuplewise-separability). This structure is effectively exploited in the new algorithm. A numerical example is given, and it is shown that all solutions are computed very rapidly.

A simple method is presented to calculate the parasitic capacitance effect in the propagation delay of series-connected MOS (SCM) structures. This method divides SCM circuits into two parts and accurately calculates the contribution of each part to the difference from the delay without parasitic capacitances.

This paper proposes a new environment for high-level VLSI design specification validation using "Algorithmic Debugging" and evaluates its benefits on three significant examples (a protocol processor, an 8-bit CPU, and a Prolog processor). A design is specified at a high-level using the structured analysis (SA) method, which is useful for analyzing and understanding the functionality to be realized. The specification written in SA is transformed into a logic programming language and is simulated in it. The errors (which terminate with an incorrect output in the simulation) included in the three large examples are efficiently located by answering junt a few queries from the algorithmic debugger. The number of interactions between the designer and the debugger is reduced by a factor of ten to a hundred compared to conventional simulation based validation methodologies. The correct SA specification can be automatically translated into a Register Transfer Level (RTL) specification suitable for logic synthesis. In this environment, a designer is freed from the tedious task of debugging a RTL specification, and can concentrate on the design itself. This environment promises to be an important step towards efficient high-level VLSI design specification validation.

We present a new multi-layer over-the-cell channel router for standard cell layout design using simulated annealing. This new approach, STANZA-M consists of two key features. The first key feature of our router is a new scheme for simulated annealing in which we use a cost function to evaluate both the total net-length and the channel heights, and an effective simulated annealing process by a limited range to obtain an optimal chnnel wiring in practical time. The second feature of our router is a basic layer assignment procedure in which we assign all horizontal wiring inside a channel to feasible layers by considering the height of channel including cell region with a one dimensional channel compaction process. We implemented our three-layer cannel router in C language on a Solbourne Series 5 Work Station (22 MIPS). Experimental results for benchmarks such as Deutsch's Difficult Example and MCNC's PRIMARY1 channel routing problems indicate that STANZA-M can achieve superior results compared to the conventional routers, and the process times are very fast despite the use of simulated annealing.

There are two approaches to implementing the international standard video coding algorithms such as H.261 and MPEG: a programmable DSP approach and a building block approach. The advantages and disadvantages of each are discussed here in detail, and the video coding algorithms and required throughput are also summarized. For more complex standard such as MPEG-, VLSI architecuture became more sophisticated. The DSP approach incorporates special processing engines and the building block approach integrates general-purpose microprocessors. Both approaches are capable of MPEG- NTSC coding in a single chip. Reduction of power consumption is a key issue for video LSIs. Architectures and circuits that reduce the supply voltage while maintaining throughput are summarized. A 0.25-µm, 3-GOPS, 0.5-W, SIMD-VSP for portable MPEG- systems could be made by using architecture-driven voltage scaling as well as feature-size scaling and SOI devices.

A single-chip architecture for three-dimensional (3-D) computer graphics (CG) is discussed assuming portable equipment with a 3-D CG interface. Based on a discussion of chip requirements, an architecture utilizing DRAM technology is proposed. A 31-Mbit, on-chip DRAM cell array allows a full-color, 480640-pixel frame with two 3-D frame buffers for double buffering and one 2-D frame buffer for superimposed or background images. The on-chip pixel generator produces R, G, B, and Z data in a triangular polygon with a zigzag-scan interpolation algorithm. The on-chip frame synthesizer combines data from one of the 3-D buffers with that from the 2-D buffer to produce superimposed or background 2-D images within a 3-D CG image. Parallel alpha-blending and Z-comparison circuits attached to the DRAM cell array provide a high data I/O rate. Estimation of the chip performance assuming the 0.35-µm CMOS design rule shows the chip size, the drawing speed, on-chip data I/O rate, and power dissipation would be 1413.5-mm, 0.25 million polygons/s, 1 gigabyte/s, and 590 mW at a voltage of 3.3 V, respectively. Based on circuit simulations, the chip can run on a 1.5-V dry cell with a drawing speed of 0.125 million polygons/s and a power dissipation of 61 mW. A scaled-down version of the chip which has an 1-kbit DRAM cell array with an attached alpha-blending circuit is being fabricated for evaluation.