This paper deals with the problems in testing large mixed-signal ICs. To help generating test patterns of these larger mixed-signal circuits for a functional test, a fast fault simulation algorithm and a fault model voltage stuck-at fault" which the algorithm is based on, are proposed. A voltage stuck-at fault is that a signal line sticks its voltage level at a certain constant. Under an assumption that blocks in a circuit are designed as identically current-independent, i.e. their input impedance can be regarded as infinite and their output impedance as zero, fault simulation can be realized by the event driven method and the concurrent method and can detect voltage stuck-at faults. These methods are essential for digital fault simulation and very effective to high speed simulation, although they were impossible for an analog or mixed-signal circuit by a conventional algorithm. Furthermore, the efficiency of the simulation is improved because I/O relation of blocks is approximated to a stepwise linear function. The above techniques and methods make fault simulation for a mixed-signal circuit possible in practical use. Actually, a fault simulator was implemented, then some test circuits were simulated. The simulator is really faster than conventional simulation based on circuit simulation. Next, fault analysis was applied to several bipolar ICs to verify the validity of the fault model voltage stuck-at faults". Analyses of open and short faults between terminals of transistors and resistors show that this fault model has sufficient coverage (more than 50%) to test mixed-signal circuit.

The applicability of Dynamic Channel Assignment methods to a Reuse Partitioning system in cellular radio systems is investigated in this paper. The investigations indicate that such a system has a tendency to increase the difference between blocking probability for the partitioning two coverage areas in comparison with the conventional Reuse Partitioning system employing Fixed Channel Assignment method. Two schemes using new Channel Rearrangement algorithms are also proposed in order to alleviate the difference as a disadvantage which gives unequal service to the system. The simulation results show that the proposed schemes are able to reduce the difference significantly while increasing the carried traffic by 10% as compared with the conventional system.

Currently there is considerable world-wide speculation regarding the introduction of optical fiber cable into access networks, because optical fiber has a big potential for providing attractive multimedia services. Since optical fiber cable can provide a variety of grade of services, high-reliability of cable networks would be required compared with the conventional copper cable networks. To develop multimedia telecommunication networks as an infrastructure, it is urgent to clarify the highly reliable optical fiber cable network architecture. Since cable network architecture deeply depends on regional conditions such as demand, area size, duct layer networks (consisting of ducts, manholes, tunnels, feeder points etc.), it is necessary to develop a cable network designing tool with user-friendly interfaces for efficiently evaluating cable network architectures. This paper firstly proposes the heuristic algorithms enhanced by the disjoint-shortest-path and the depth-first-search methods that would be applicable for real access networks. Secondly, the design method of highly reliable optical fiber cable network based on the heuristic algorithms in terms of network cost and unavailability caused by cable breakdown is proposed. It can design the combination of star- and loop-shaped (where two diversified routes exist between a feeder point and central office) cable network. Furthermore, comparison with the conventional design method which simply applies star- or loop-shaped cable network is done in terms of economy and reliability on real access networks in the Tokyo metropolitan area. It is concluded that the proposed method can reduce the network cost further and realize a short unavailability value compared with the conventional method.

An optimum design scheme for logical network topologies on a Flexible Multi-QoS Logical ATM Network, named Full-Net, is proposed. Full-Net offers high-quality Virtual-Path (VP) networks and controls end-to-end QoS only at the VP-network's access points. To develop the optimum network topology for multimedia traffic in a single ATM network, a logically con figured Virtual Channel Handler (VCH) interconnection network is associated with each QoS class. Many logical networks can be mapped at the same time on the same network, because mapping is independent of the network's physical implementation. To achieve an optimum design scheme for logical networks, the number of disjoint routes is introduced as the parameter used to optimize logical network topology. The number of disjoint routes is chosen so as to maximize total network efficiency. The optimum number of disjoint routes depends on the required QoS, VC-traffic characteristics, and traffic demand. By choosing the relevant cost characteristics, the network operator can easily maximize network efficiency and provide customers with the QoS they request at minimum cost. The proposed optimum multi-QoS network design scheme on a Full-Net architecture is an efficient solution to implementing multi-QoS control in an ATM network.

In the correspondence discrete Wigner higher order spectra (WHOS) of harmonizable random signals are addressed and their relations with polyspectra (HOS) are illustrated. It is shown, that discrete WHOS of a random stationary signal do not reduce to the aliased polyspectra in a similar way as Wigner distribution (WD) reduces to the power spectrum of a random signal. Wigner 2nd-order time-frequency distribution of deterministic signals and the 3rd-order spectrum of stationary signals are presented in their modified forms to be used to estimate time-varying third-order spectrum of discrete nonstationary random harmonizable processes.

The goal of this paper is to propose a new symbolic model checking approach named time-space modal model checking, which could be applicable to verification of bit-slice microprocessor of infinite bit width and one dimensional systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.

Current testing has been proposed as an alternative technique for testing fully CMOS digital LSIs. Current testing has higher fault coverage than conventional stuck-at fault (SAF) testing and is more economical because it detects a wide range of faults and requires fewer test vectors than does SAF testing. We have proposed a current testing that measures the integral of the power supply current (IDD) during one clock period including the switching current. Since this method cannot be affected by the switching current, it can be used to test an LSI operating at a relatively high clock freuqnecy. This paper presents an improved current testing method for CMOS digital and analog LSIs. The method uses two current values (i.e., an upper limit and a lower limit) and judges the circuit under test to be faulty if the measured IDD is outside these limits. The proposed current testing is evaluated here for some kinds of faults (e.g., the bridging fault and the breaking fault) in digital and mixed-signal LSIs, and its efficiency of the current testing using SPICE3.

A novel algorithm, as an advanced Hybrid Channel Assignment strategy, for channel assignment problem in a cellular system is proposed. A difference from the conventional Hybrid Channel Assignment method is that flexible fixed channel allocations which are variable through the channel assignment can be performed in order to cope with varying traffic. This strategy utilizes the Channel Rearrangement technique using the artificial neural network algorithm in order to enhance channel occupancy on the fixed channels. The strategy is applied to two simulation models which are the spatial homogeneous and inhomogeneous systems in traffic. The simulation results show that the strategy can effectively improve blocking probability in comparison with pure dynamic channel assignment strategy only with the Channel Rearrangement.

This paper describes an innovative heat-pipe cooling technology for asynchronous transfer mode (ATM) switching multichip modules (MCMs) operating with a throughput of 40 Gb/s. Although high-speed ATM link-wires are connected at the top surface of the MCMs, there is no room to cool the MCM by forced air convection, because power and the system clock signal are supplied by connectors on the rear and periphery of the MCM. We therefore chose to attach a cold-plate to the back of each MCM. The condenser part of the heat pipe, which is mounted behind the power supply printed circuit board, is cooled by low-velocity forced air. Total power dissipation is about 30 watts per MCM. With a 2 m/s foreced airflow, the sub-switching-element module (four MCMs) operates at a throughput of 80 Gb/s with a maximum junction temperature of less than 85. Measured thermal resistance between the switch LSI junction and air is about 6/W. This heat-pipe cooling system has a small system footprint, compact hardware, and good cooling capacity.

Reducing switching noise is a key point in increasing signal transmission capability. This noise is related to the pin assignment of connectors and the inner layer structure of the printed circuit board (PCB). This paper presents and evaluates experimental results on the relationships between pin assignment, the number of the signal outputs, and switching noise. It shows that calculated and experimental results agree well if we assume that the distribution of return current, causing switching noise in a connector, does not uniformly decrease with increases in the number of ground pins. We also assume that the effective number of ground pins is related to the number of signal pins even if there are more ground pins than there are signal pins.

The recursive least-squares filter and fixed-point smoother are designed in linear discrete-time systems. The estimators require the information of the system matrix, the observation vector and the variances of the state and white Gaussian observation noise in the signal generating model. By appropriate choices of the observation vector and the state variables, the state-space model corresponding to the ARMA (autoregressive moving average) model of order (n,m) is introduced. Here,some elements of the system matrix consist of the AR parameters. This paper proposes modified iterative technique to the existing one regarding the estimation of the variance of observation noise based on the estimation methods of ARMA parameters in Refs. [2],[3]. As a result, the system matrix, the ARMA parameters and the variances of the state and observation noise are estimated from the observed value and its sampled autocovariance data of finite number. The input noise variance of the ARMA model is estimated by use of the autocovariance data and the estimates of the AR parameters and one MA parameter.

This paper reviews very high-speed optical signal processing technology based on the instantaneous characteristic of optical nonlinearities. Focus is placed on 100-Gbit/s optical time-division multiplexing (TDM) transmission systems. The key technologies including ultrashort optical pulse generation, all-optical multiplexing/demultiplexing and optical timing extraction techniques are alse described together with their major issues and future prospects.

When communication network planning-design is performed, especially in a short-term case, it is important to utilize existing facilities in the construction of the new network. In this paper, link capacity assignment problem (CA problem) for packet-switched networks is investigated with the consideration of the existing network. To deal with this, per-unit cost of existing link capacity is thought to be less than that of newly installed capacity and a link cost function is modeled by a non-linear, non-differentiable one which is composed of two portions of capacity cost. After formulating the CA problem, two optimum algorithms derived from Lagrange multiplier method are presented and a modified algorithm is used for solving the CA problem in order to reduce the computation time. Some numerical results show that according to the values of link traffic flows, there will be links whose capacities must be set equally to the existing values. Moreover, when link cost difference is introduced in the CA problem, the number of links that the capacities of which have to be changed from existing values is less than that of linear cost function case, i.e., the case without consideration of the cost difference in link capacity.

A new approximation calculation method, named the Recursive Matrix-calculation (RM) method, is proposed. It uses matrix calculation to determine the number of link disjoint paths under a hop link number constraint, i.e. hop limit. The RM method does not overestimate the number of link disjoint paths. When networks are designed by this method, network reliability is perfectly guaranteed. Moreover, the RM method is based on matrix calculation, so CPU time can be reduced by using super-computers equipped with vector processors. Simulation results confirm that the RM method yields rapid approximations that are conservative. Thus the proposed method is very useful for designing reliable multimedia networks.

We describe a formal verification algorithm for pipelined processors. This algorithm proves the equivalence between a processor's design and its specifications by using rewriting of recursive functions and a new type of mathematical induction: extended recursive induction. After the user indicates only selectors in the design, this algorithm can automatically prove processors having more than 10(1010) states. The algorithm is manuary applied to benchmark processors with pipelined control, and we discuss how data width, memory size, and the numbers of pipeline stages and instructions influence the computation cost of proving the correctness of the processors. Further, this algorithm can be used to generate a pipeline invariant.

Board-to-board signal transmission in a rack system is affected by various types of noise. Signal transmission capability is evaluated on the basis of physical construction parameters and signal conditions, such as rise time and amplitude. This paper examines noise in a rack system and shows that the maximum single-ended transmission capability is 100Mbps when pin-type connectors are used with a signal/ground pin assignment ratio of 1/1.

Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.

Optical path technology that employs both WDM/FDM and wavelength routing will play a key role in supporting future high bandwidth transport networks. WP/VWP (Wavelength Path/Virtual Wavelength Path) technologies are very effective in realizing optical path networks. In these networks, since photonic wavelengths are scarce resources, the number of wavelengths required to construct the network must be minimized. However, the wavelength assignment problem, minimizing the number of wavelengths, is an NP-complete problem. Solving this problem heuristically is an important issue for designing large-scale WP/VWP based networks that are also practical. To realize optical path networks, we need to develop path accommodation design algorithms that heuristically solve the wavelength assignment problem. This paper proposes novel path accommodation design algorithms for WP/VWP networks that minimize the number of wavelengths required. We numerically elucidate that the numbers of wavelengths required for active WPs and VWPs are almost equal. When link failure restoration is considered, they are different; more wavelengths are needed with the WP scheme than with the VWP scheme. It is also demonstrated that the proposed algorithms are applicable to a large scale network design.

This paper describes an exact symbolic formulation of resource-constrained scheduling which allows speculative operation execution in arbitrary forward-branching control/data paths. The technique provides a closed-form solution set in which all satisfying schedules are encapsulated in a compressed OBDD-based representation. An iterative construction method is presented along with benchmark results. The experiments demonstrate the ability of the proposed technique to efficiently extract parallelism not explicitly specified in the input description.

A key element in the CDMA transmission is DS spreading. Spreading in a DS/SSMA system are provided in two categories-synchronization and data. For synchronization sequences, good auto-correlation and cross-correlation properties are required in order to guarantee fast acquistion with a minimum false alarm probability. On the other hand, the auto-correlation property may not be so important in data spreading since synchronization is obtained by synchronization spreading. In this paper we provide a set of synchronization sequences and a set of data sequences--each a set of binary N-tuples--that have the necessary correlation constraints.