This paper presents a delivery mechanism using a spectrum delivery switch (SDS) in a microcell system. In our fiber-optic microcell systems, modulators, demodulators and spectrum delivery switches are installed in a central station. A spectrum delivery switch controls provide flexible dynamic channel assignment and functions as a hand over algorithm. This control method employs a TDMA time slot switch and a MODEM connection switch. The relation between blocking probability and offered traffic are described and computer simulation results are shown. The results indicate an improvement in this blocking probability over conventional systems.

This paper analyses the amplification characteristics of a two-loop controlled switching power amplifier for a digital portable telephone and presents the amplifier which has a flat gain and small phase delay from dc to 100kHz. This amplifier is a modification of a switching regulator and it uses two-loop control to achieve a wideband amplification characteristic. Optimum amplification characteristics, however, can't be designed by using the conventional method for designing a switching regulator because a flat gain and small phase delay in an amplification characteristic has not been considered for most switching regulators. This paper analyses in detail the small-signal transfer functions of the switching power amplifier and shows the behaviour of zero and poles. It also shows the boundary condition of large-signal operation. A new design procedure of a switching power amplifier is presented, and the analytical results are verified by experiments.

A new applicative design language is proposed for developing generators of data-path modules from hardware algorithms. The language includes a set of primitives that represent placement operations, parameterized cells, routing patterns and a set of transformation rules specifying modifications of the module topology without changing its functionality. Using the language, a hardware algorithm designer can easily define both the topological and geometrical specifications of module generation directly at the functional level without engaged in the layout details. A sketch of the language and an example of module design with the language is presented.

System and chip synthesis must evaluate candidate Register-Transfer (RT) architectures with respect to finished physical designs. Current RT level cost measures, however, are highly simplified and do not reflect the real physical disign. Complete physical design, on the other hand, is quite costly, and infeasible to be iterated many times. In order to establish a more realistic assessment of layout effects, we propose a new layout model which efficiently accounts for the effects of wiring and floorplanning on the area and performance of RT level designs, before the physical design process. Benchmarking has shown that our model is quite accurate.

This paper presents a description and an analysis of three standard" hardware description languages (HDLs): Very High Speed Integrated Circuit HDL (VHDL), Verilog-HDL, and Unified Design Language for Integrated Circuits (UDL/I), Kyoto University Education Chip (KUE-Chip) is used as a design benchmark to compare the features and syntax of VHDL, Verilog-HDL, and UDL/I.

Test pattern generation is getting much harder as the circuit size becomes larger. One problem is that it tends to take much time and another one is that it is difficult to detect redundant faults. Aiming to cope with these problem, an enhanced unique sensitization technique is proposed in this paper. This powerful global implication reduces the number of backtracks with reasonable computational time. And a fast test pattern generator featuring this unique sensitization demonstrates its performance using large benchmark circuits with over ten thousands of gates. It takes only a minute to detect all testable faults and to identify all redundant faults of 20,000 gates circuit on a workstation.

We introduce automatic procedures for generating and verifying sufficient correctness properties of synchronous processors. The targeted circuits are synchronous array processors designed from localized, highly regular data dependency graphs (DDGs). The specification, in the form of a DDG, is viewed as a maximally parallel circuit. The implementation, on the other hand, is a (partially) serialized circuit. Since these circuits are not equivalent from an automata-theoretic viewpoint, we define the correctness of the implementation against the specification to mean that a certain relation (called the β-relation) holds between the two. We use a compositional approach to decouple the verification of the control circuitry from that of the data path, thereby gaining efficiency. An array processor in isolation may not have a definite flow of control, because control may reside in the data stream. Therefore, for the purpose of verification, we construct an auxiliary machine, which keeps a timing reference and generates control signals abstracted from a typical data stream. Sufficient correctness conditions are expressed as past-tense computation tree logic (CTL) formulae and verified by CTL model-checking procedures. Experimental results of the verification of a matrix multiplication array and a Gaussian elimination array are presented.

A model for a large network with an unidirectional linear respone (ULR) is proposed in this letter. This deterministic system has powerful computing properties in very close correspondence with earlier stochastic model based on McCulloch-Pitts neurons and graded neuron model based on sigmoid input-output relation. The exclusive OR problems and other digital computation properties of the earlier models also are present in the ULR model. Furthermore, many analog and continuous signal processing can also be performed using the simple ULR neural network. Several examples of the ULR neural networks for analog and continuous signal processing are presented and show extemely promising results in terms of performance, density and potential for analog and continuous signal processing. An algorithm for the ULR neural network is also developed and used to train the ULR network for many digital and analog as well as continuous problems successfully.

We present algorithms for the optimization of sequential synchronous digital circuits using structural model, i.e. interconnections of combinational logic gates and synchronous registers. This approach contrasts traditional methods using state diagrams or transition tables and leveraging state minimization and encoding techniques. In particular, we model circuits by synchronous logic networks, that are weighted multigraphs representing interconnections of gates implementing scalar combinational functions. With this modeling style, area and path delays are explicit and their variation is easy to compute when circuit transformations are applied. Sequential logic optimization may target cycle-time or area minimization, possibly under area or cycle-time constraints. Optimization is performed by a sequence of transformations, directed to the desired goal. This paper describes the fundamental mechansms for transformations applicable to sequential circuits. We review first retiming and peripheral retiming techniques. The former method optimizes the position of the registers, while the latter repositions the registers to enlarge maximally the combinational region where combinational restructuring algorithms can be applied. We consider then synchronous algebraic and Boolean transformations, that blend combinational transformations with local retiming. Both classes of transformations require the representation of circuits by means of logic expressions with labeled variables, the labels representing discrete time-points. Algebraic transformations entail manipulation of time-labeled expressions with algebraic techniques. Boolean transformations exploit the properties of Boolean algebra and benefit from the knowledge of don't care conditions in the search for the best implementation of local functions. Expressing don't care conditions for sequential circuits is harder than for combinational circuits, because of the interaction of variables with different time labels. In addition, the feasibility of replacing a local function with another one may not always be verified by checking for the inclusion of the induced perturbation in local explicit don't care set. Indeed, the behavior of sequential circuits, that can be described appropriately by the relation between input and output traces, may require relational models to express don't care conditions. We describe a general formalism for sequential optimization by Boolean transformations, where the don't care conditions are expressed implicitly by synchronous recurrence equations. We present then an optimization method for this model, that can exploit degrees of freedom in optimization not possible for other methods, and hence providing solutions of possible superior quality. We conclude by summarizing the major features and limitations of optimization methods using structural models.

This paper describes the hierarchical behavioral description language celled SFL and its processing system. This integrated CAD system called PARTHENON is used for designs of the leading ASICs in the NTT Systems Labs. This paper shows, therefore, the effectiveness of PARTHENON as a practical high-lelel synthesis system through real design experience. SFL was developed to aid in the design of the hardware functions and behaviors of ASICs composed solely of clocksynchronized circuits. The main features of SFL are as follows: (1) It is not mixed with connection description, but employs only behavioral description (like procedual description in program language), and it provides hierarchical expression of behavioral description. (2) It permits the description of parallel processing operations by adopting a new hardware task concept. And, (3) it is linked with the behavioral simulator, logic synthesizer, and other components of the processing system. After describing SFL in some detail, a brief explanation of its synthesizer and other processing components is provided, along with its application results in the real design of some leading ASICs at the NTT Systems Laboratories.

This paper proposes a technique for estimating speech parameters in noisy environment. The technique uses a spectral model represented by generalized cepstrum and estimates the generalized cepstral coefficients from the speech which has been degraded by additive background noise. Parameter estimation is based on maximum a posteriori (MAP) estimation procedure. An iterative approach which has been formulated for all-pole modeling is applied to the generalized cepstral modeling. Generalized cepstral coefficients are obtained by an iterative procedure that consists of the unbiased estimation of log spectrum and noncausal Wiener filtering. Since the generalized cepstral model includes the all-pole model as a special case, the technique can be viewed as a generalization of the all-pole modeling based on MAP estimation. The proposed technique is applied to the enhancement of speech and several experimental results are also shown.

A new trial of statistical evaluation for an output response of power linear type acoustic systems with nonstationary random input is proposed. The purpose of this study is to predict the output probability distribution function on the basis of a standard type pre-experiment in a laboratoty. The statistical properties like nonstationarity, non-Gamma distribution property and various type linear and non-linear correlations of input signal are reflected in the form of differential operation with respect to distribution parameters. More concretely, the pre-experiment is carried out for a power linear acoustic system excited only by the Gamma distribution type sandard random input. Considering the non-negative random property for the output response of a power linear system, the well-known statistical Laguerre expansion series type probability expression is first employed as the framework of basic probability distribution expression on the output power fluctuation. Then, the objective output probability distribution for a non-stationary case can be easily derived only by successively employing newly introduced differential operators to this basic probability distribution of statistical Laguerre expansion series type. As an application to the actual noise environment, the proposed method is employed for an evaluation problem on the stochastic response probability distribution for an acoustic sound insulation system excited by a nonstationary input noise.

This paper describes a new automated approach to generating the patterns of CMOS leaf cells from transistor-level connectivity data. This method can generate CMOS leaf cells that are configurable to a macro cell satisfying user-specified constraints. The user-specified constraints include the aspect ratio and port positions of the macro cell. We propose a top-down method for converting the macro cell level constratints to leaf cell level ones. Using this method, a variety of customized macro cells can be designed in a short turn-around time. The method consists of four processes--diffusion sharing, initial placement, placement improvement and routing--which culminate in the automatic generation of symbolic representations. Using a compactor, those symbolic representations can be converted to physical patterns which are gathered into a macro cell by a macro generator. We define various objective functions to improve unit pair placement. We also introduce five ways to optimize leaf cell area: 1) multi-row division, 2) gate division 3) rotation, 4) power line and diffusion overlapping and 5) reconstruction of hierarchical structure. The proposed approach has been applied to various kinds of CMOS leaf cells. Experimental results show that the generated cells have almost the same areas as those generated by conventional bottom-up approaches in leaf and macro cell layouts. This approach offers a further advantage in that the various-sized macro cells required by layout disigners can also be generated.

It is concluded from numerical examples for the well-known linear PN sequence families of a large range of periods that the mean-square cross-correlation value between sequences is the dominating parameter to the average signal-to-noise power ratio performance of an asynchronous direct-sequence (DS) code-division multiple-access (CDMA) system. The performance parameters derived by Pursley and Sarwate are used for numerical evaluation and the validity of conclusion is supported by reviewing the other related works. The mean-square periodic cross-correlation takes the equal value p (code period) for the known CDMA code families. The equal mean-square cross-correlation performance results from the basic results of coding theory.

In this paper, an optimized wideband channel sounder designed for measuring the time variant impulse response of outdoor radio channels in the frequency range 1800-2000 MHz is presented. Prior to hardware implementation the system was first modelled on a high performance supercomputer to enable the system designer to optimize the digital signal processing algorithms and the parameters of the hardware components by simulation. It is shown that the proposed measuring system offers a significantly larger amplitude resolution, i.e. dynamic range, than conventional systems applying matched filtering. This is achieved by transmitting digitally generated periodic spread spectrum test signals adjusted to amplifier non-linearities and by applying optimum unbiased estimation instead of matched filtering in the receiver. A further advantage of the hardware implementation of the proposed system compared to conventional systems [5]-[7] is its high flexibility with respect to measuring bandwidth, period of the test signal and sounding rate. The main features of the optimized system are described and first measurement results are presented.

A new circuit design of Josephson ternary δ-gate composed of Josephson junction devices is presented. Mathematical theory for synthesizing, analyzing, and realizing any given function in ternary system using Josephson ternary δ-gate is introduced. The Josephson ternary δ-gate is realized using SQUID technique. Circuit simulation results using J-SPICE demonstrated the feasibility and the reliability operations of Josephson ternary δ-gate with very high performances for both speed and power consumption (max. propagation delay time44 ps and max. power consumption2.6µW). The Josephson ternary δ-gate forms a complete set (completeness) with the ternary constants (1, 0, 1). The number of SQUIDs that are needed to perform the operation of δ-gate is 6. Different design with less than 6 SQUIDs is not possible because it can not perform the operation of δ-gate. The advantages of Josephson ternary δ-gate compared with different Josephson logic circuits are as follows: The δ-gate has the property that a simple realization to any given ternary logic function as the building blocks can be achieved. The δ-gate has simple construction with small number of SQUIDs. The δ-gate can realize a large number of ternary functions with small number of input/output pins. The performances of δ-gate is very high, very low power consumption and ultra high speed switching operation.

In multidimensional signal sampling, the orthogonal sampling scheme is the simplest one and is employed in various applications, while a non-orthogonal sampling scheme is its alternative candidate. The latter sampling scheme is used mainly in application where the reduction of the sampling rate is important. In three-dimensional (3-D) signal processing, there are two typical sampling schemes which belong to the non-orthogonal samplings; one is face-centered cubic sampling (FCCS) and the other is body-centered cubic sampling (BCCS). This paper proposes a new design method for 3-D band-limiting FIR filters required for such non-orthogonal sampling schemes. The proposed method employs the McClellan transformation technique. Unlike the usual 3-D McClellan transformation, however, the proposed design method uses 2-D prototype filters and 2-D transformation filters to obtain 3-D FIR filters. First, 3-D general sampling theory is discussed and the two types of typical non-orthogonal sampling schemes, FCCS and BCCS, are explained. Then, the proposed design method of 3-D bandlimiting filters for these sampling schemes is explained and an effective implementation of the designed filters is discussed briefly. Finally, design examples are given and the proposed method is compared with other method to show the effectiveness of our methos.

This paper discusses the performance of asynchronous direct-sequence spread-spectrum multiple-access systems using binary or quaternary phase-shift keyed signals with the strict bandwidth-limitation by Nyquist filtering. The signal-to-noise plus interference ratio (SNIR) at the output from the correlation receiver is derived analytically taking the cross-correlation characteristics of spreading sequences into account, and also an approximated SNIR of a simple form is presented for the systems employing Gold sequences. Based on the analyzed result of SNIR, bit error rate performance and spectral efficiency are also estimated.

An asynchronous spread spectrum (SS) wireless modem has been implemented using an efficient ZnO-SiO2-Si surface acoustic wave (SAW) convolver. The modem is based on a direct-sequence/frequency-shift-keying (DS/FSK) method for the modulation. The demodulation is carried out asynchronously utilizing the coherent correlation characteristics of the SAW convolver. In order to improve the narrowband interference rejection capability, we propose a new technique based on the reference signal control. A notched-reference-signal circuit and a self-convolution canceler are implemented in the SS modem for the reference signal control. It was found that the antijam capability for narrowband interference is at least -24dB of desired-to-undesired power ratio (D/U); the improvement of the antijam capability is 16dB up as compared with our previous SS modem.

This paper presents a new redundant fault identification algorithm, REDUCT. This algorithm handles the redundant fault identification problem by transforming a given circuit into another circuit. It also reduces the complexity of the transformed circuit, which is caused by a large number of reconvergences and head lines, using five circuit reduction techniques. Further, it proves redundancies and generates test patterns for hard faults more efficiently than conventional test pattern generation algorithms. We obtained 100% fault coverage for all ISCAS85 benchmark circuits using REDUCT following the execution of the test pattern generation algorithm N2-V.