Net-Oriented Analysis and Design (NOAD) is defined as three items: (1) Various nets are utilized as an effective modeling method. (2) Inter-relationships among verious nets are determined. (3) Verification or analysis methods for nets are provided and they are implemented based on the mathematical theory, that is Net theory. Very few methods have been presented to satisfy these three items. For example, the Real-Time SA method covers item (1) only. The Object-Oriented Analysis and Design method (OOA/OOD) covers items (1) and (2). NOAD can be regarded as an extension to OOA/OOD. This paper discusses how effectively various nets have been used in actual software development support metnods and tools and evaluates such several methods and tools from the NOAD viewpoint.

This paper deals with the sub-problems of generating a mask pattern from the logical description of a large-scale CMOS circuit. The large-scale layout can be generated in divide-and-conquer style: divide a given circuit into a set of sub-circuits, generate the layout of each sub-circuit, and merge the resulting layouts to create the whole layout. This paper proposes a layout synthesis algorithm for a sub-circuit with physical constraints for the synthesis scheme above. The physical constraints considered here are the relative placement of logic cells (sets of logic gates) and the routing constraint based on the costs of wiring layers and vias. These constraints will be given by the global optimizer in a two-dimensional layout synthesis routine, and they should be kept at the subsequent one-dimensional layout synthesis for a sub-circuit. The latter is also given for enhancing the circuit performance by limiting the usage of wiring layers and vias for special net such as a clock net. The placement constraint is maintained using PQ-tree, a tree structure representing a set of restricted permutations of elements. One-dimensional layout synthesis determines the placement of transistors by the enhanced pairwise exchanging method under the PQ-tree representation. The routing constraints is considered in the newly developed line-search routing method using a cost-based searching. Experimental results for practical standard cells, including up to 200 transistors, prove that the algorithms can produce the layouts comparable to handcrafted cells. Also on a two-dimensional layout synthesis using the algorithms, the results for benchmark circuits of Physical Design Workshop 1989, i.e., MCNC benchmark circuits, are superior to the best results exhibited at Design Automation Conference 1990.

GaAs MESFETs with a p-buffer layer (or a buried p-layer) are important devices for high-speed GaAs ICs. To study what conditions are required as a good substrate for ICs, we have investigated, by two-dimensional simulation, small-signal parameters and drain-current transients of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate. It is shown that the introduction of a p-buffer layer is effective to improve the transconductance and the cuttoff frequeycy. These parameters are not degrade even if the p-layer doping is increased and a neurtral p-region exists. It is also shown that drain-current drifts and hysteresis in I-V curves can occur in a case with a p-buffer layer, too. It is concluded that the introduction of a relatively highly-doped p-layer on a substrate with low acceptor and electron trap (EL2) densities is effective to realize the stable and high performance of GaAs MESFETs.

In recent VLSI design of digital data paths, significantly more area is occupied by interconnect elements than by functional units and registers. Nevertheless, until recently most work in data path synthesis has been concentrated on trying to reduce the area of functional units and registers, without paying much attention to the interconnect area. Lately, research that addresses reducing the area of interconnection and of functional units and registers is increasing, but in them, most algorithms for assigning interconnect elements are not efficient enough to optimize the interconnect area. In most current research, algorithms for interconnect element assignment are used to calculate the cost functions during the scheduling and/or allocation steps. This makes it impossible to use efficient optimization algorithms that may consume long time. This paper presents some new algorithms used to assign interconnect elements in data paths. The algorithms minimize the number of multiplexer inputs after the scheduling and operator/register allocations have been made. The algorithms have two characteristics. First, we use a branch and bound method for small problems. We confirmed that exact solutions in practical time can be obtained with this method for rather large problems, when the solutions are restricted to a one-level multiplexer model. Second, we use a certain heuristic method for larger problems. The algorithms have been implemented in C on an Apollo Domain Series 10000.

The detection problem of fluctuating radar targets in the presence of interference (noise and clutter) is considered; the assumed model for both target and clutter is a zero-mean stationary Gaussian random process with assigned power spectral densities. The pertaing optimum linear processor, namely the Optimized Filtering, is derived and its performance are evaluated in different operating conditions, including mismatching with the designed model. Finally, comparison with filtering techniques designed for targets with zero spectral width, i.e. the Moving Target Detector, are performed.

This paper describes MENDELS ZONE, a Petri-net-based concurrent programming environment, which is especially suitable for cooperating discrete event systems. MENDELS ZONE adopts MENDEL net, which is a type of high level (hierarchical colored) Petri net. One of the characteristics of the MENDEL nets is a process-oriented hierarchy like CCS, which is different from the subnet-oriented hierarchy in the Jensen's hierarchical colored Petri net. In a process-oriented hierarchy, a hierarchical unit is a process, which is more natural for cooperating and decentralized discrete event control systems. This paper also proposes a design methodology for MENDEL nets. Although many Petri net tools have been proposed, most tools support only drawing, simulation, and analysis of Petri nets; few tools support the design methodology for Petri nets. While Petri nets are good final design documents easy to understand, analyzable, and executable it is often difficult to write Petri nets directly in an earlier design phase when the system structure is obscure. A proposed design methodology makes a designer to construct MENDEL nets systematically using causality matrices and temporal logic. Furthemore, constructed MENDEL nets can be automatically compiled into a concurrent programming language and executed on a parallel computer.

The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. With the delay time of logic elements such as TTL SN7400, the minimum delay time (dm), the maximum delay time (dM), and the typical delay time are specified in the manual, and the delay time of an element is one in the interval between dm and dM. Here we assume a discrete time, and we manipulate the variance of the delay time as a set of output strings corresponding to each delay time. We call the model as the combined delay model. Since many output strings are generated with a single input string, the usual timing simulation method cannot be applied. We propose a timing verification method using a behavior extraction method of logic circuits with respect to a time string set: with respect to the specified input set, the method extracts the output string set of each element in the circuit. We devised (1) a mechanism to keep the correspondence between a primary input string and an output string with respect to the primary input string, (2) a mechanism to manipulate the nondeterminism included in the combined delay model, and (3) an event-driven like data compaction method in representing finite automata. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuit with 100 elements or so. The method includes the state explosion, but the data compaction method and the extraction for only the specified input set are useful to control the state explosion.

In case of the system identification problem, such as an echo canceller, estimated impulse response obtained by the frequency-domain adaptive filter based on the circular convolution has estimation error because the unknown system is based on the linear convolution in the time domain. In this correspondence, we consider a sufficient condition to reduce the estimation error.

It is well known that the multiple-valued signed-digit (SD) arithmetic circuits have the attractive features of compactness and high-speed operation. However, both of these features have yet to be utilized fully. In this paper, we consider the application of a parallel-structure-based VLSI processor. A high-performance parallel-structure-based multiple-valued VLSI processor using the radix-2 SD number system is proposed. Its compactness makes the parallelism high under chip size limitations in comparison with the ordinary binary arithmetic circuits. Moreover, the speed of the single arithmetic module is very high in the SD arithmetic circuits, so that we can take advantage of the high-speed operation in the parallel-structure-based VLSI processor chip. The multiple-valued bidirectional current-mode technology is used not only in high-speed small sized arithmetic circuits, but also in reducing the number of connections in the parallel-structure-based VLSI processor. The proposed processor is specially developed for real-time digital control, where the performance is evaluated by delay time. Performance estimation using SPICE simulators shows that the delay time of proposed processor for matrix operations such as matrix multiplication is greatly reduced in comparison with a conventional binary processor.

A new image restoration filter based upon a physical model of an image degradation is constructed. By means of this filter, signal dependent noise and blur can be suppressed. In particular, image degradation noise can be modeled in generalized form. Noise suppression and deblurring are performed separately. This filter has additional applications when used in conjunction with the degradation model, such as real photographic images and photoelectronic images. Simulation results show that this filter gives a superior performance in restoring an image degraded by signal dependent noise and blur.

It often occurs in the acoustic environment that a specific signal is contaminated by the additional noise of non-Gaussian distribution type. In order to extract exactly the various statistical information of only specific signal from the observed noisy data, a stochastic signal processing by use of digital computer is essential. In this study, a stochastic method for estimating the probability function of the specific signal embedded in the additional noise is first theoretically proposed in a suitable form for the quantized level observation. Then, the effectiveness of the proposed method is experimentally confirmed by applying it to the observed data in the acoustic environment.

This paper proposes a hierarchical Digital Signal Processor (DSP) Code Generator VIRGO for large scale general signal processing algorithms. Hierarchical structured Vectorized Signal Flow Graph (V-SFG) description is used as input specifications. Ths DSP independent optimization procedure for both the program size and the execution time is performed each module by each hierarchically with regard to operation order, memory assignment and register allocation. The efficient code generation is demonstrated by comparing both instruction steps and dynamic steps of a practical ADPCM encoder/decoder with a conventional method.

It often occurs in an environmental phenomenon in our daily life that a specific signal is partially or completely contaminated by the additional external noise. In this study, a digital filter for estimating a specific signal fluctuating impulsively under the existence of an actual external noise with various kinds of probability distribution forms is proposed in an improved form of already reported digital filter. The effectivenss of the proposed theory is experimentally confirmed by applying it to the estimation of an actual impulsve signal in a room acoustic.

Telecommunication services are accomplished by cooperative networks of widely distributed communication processes and service users. Those specifications are often modeled by a set of possible message sequences among cooperating processes and users. The distributed and cooperative nature of telecommunication services results in a wide variety of message sequences and makes it more difficult for service designers to design such telecommunication services. To mitigate the difficulty, we propose a design support system with MSRs (message sequence rules) as design knowledge. The system supports the following two design activities: (1) specification of a typical message sequence that corresponds to a service behavior in a successful case, and (2) specification of incidentally possible message sequences that involve service behaviors in successful and unsuccessful cases. For the former activity, the system interacts with designers and identifies the messages they give with MSRs to understand the context of the message sequence and suggest possible subsequent messages. For the latter activity, the system applies MSRs to the typical message sequence and reasons possible messages from/to relevant processes and users under every state to suggest incidentally possible message sequences. Accordingly, designers may be relieved of investigating a wide variety of service behaviors in successful and unsuccessful cases. The system capability is based on MSRs equivalent to reusable message sequence components. MSRs can be obtained through abstraction of implementation-dependent messages and decomposition of those sequences into temporal relations among messages. The rule acquisition method provides MSRs with the potential to generate a wide variety of message sequences. In order to verify rule applicability, we have experimentally designed three kinds of services and conducted an experimental rule application to those specifications. The experimental evaluation results indicate that applicability is fairly high.

Fast wavelet transform is presented for realtime processing of wavelet transforms. A processor for the fast wavelet transform is of the frequency sampling structure in architectural level. The fast wavelet transform owes its parallelism both to the frequency sampling structure and parallel tapping of a series of delay elements. Computational burden of the fast transform is hence independent of specific scale values in wavelets and the parallel processing of the fast transform is readily implemented for real-time applications. This point is quite different from the computation of wavelet transforms by convolution. We applied the fast wavelet transform to detecting detonation in a vehicle engine for precise real-time control of ignition advancement. The prototype wavelet for this experiment was the Gaussian wavelet (i.e. Gabor function) which is known to have the least spread both in time and in frequency. The number of complex multiplications needed to compute the fast wavelet transform over 51 scales is 714 in this experiment, which is less than one tenth of that required for the convolution method. Experimental results have shown that detonation is successfully detected from the acoustic vibration signal picked up by a single knock sensor embedded in the outer wall of a V/8 engine and is discriminated from other environmental mechanical vibrations.

A 1/2 frequency divider using resonant-tunneling hot electron transistors (RHETs) has been proposed and demonstrated. The circuit make the best use of negative differential conductance, a feature of RHETs, and contains one half transistors than used in conventional circuits. The RHETs were fabricated using self-aligned InGaAs RHETs and WSiN thin-film resistors on a single chip. The RHETs have an i-InGaAlAs/i-InGaAs collector barrier that improves the current gain at low collector-base voltages. Circuit operation was confirmed at 77 K.

This paper proposes a new design method of variable FIR digital filters. The method uses a multi-dimensional linearphase FIR filter as a prototype. The principle of the proposed method is based on the fact that the crosssectional characteristics of a 2-D filter along with a line vary if the intersection of this line is changed. The filter characteristics can be varied by recalculating all the filter coefficients from proposed equations, which leads to an advantage that the variable range is very wide. Another advantage is that the passband and stopband deviations are completely predetermined in the design procedures and that the passband edge can be accurately settled to a desired frequency while keeping the transition band width unchanged. First the proposed design method is explained and the effect of the transition band of 2-D filters is discussed. Then the calculation cost required in updating the filter coefficients are considered. Finally two design examples are presented and the proposed method is compared with the existing one, which shows the usefulness of our method.

In this paper, a new description of a separable-denominator (S-D) two-dimensional (2-D) transfer matrix is proposed, and its realization is considered. Some of this problem had been considered for the transfer matrices whose elements are two-variables rational functions. We shall propose a 2-D transfer matrix whose inputs-outputs relation is represented by a ratio of two-variables polynomial matrices, and present an algorithm to obtain a 2-D state-space model from it. Next, it is shown that the description proposed in this paper is always minimally realizable. And, we shall present a method of obtaining the description proposed in this paper from a S-D 2-D rational transfer matrix.

This paper describes a super high definition (SHD) image processing system we have developed. The computing engine of this system is a parallel processing system with 128 processing elements called NOVI- HiPIPE. A new pipelined vector processor is introduced as a backend processor of each processing element in order to meet the great computing power required by SHD image processing. This pipelined vector processor can achieve 120 MFLOPS. The 128 pipelined vector processors installed in NOVI- HiPIPE yield a total system peak performance of 15 GFLOPS. The SHD image processing system consists of an SHD image scanner, and SHD image storage node, a full color printer, a film recorder, NOVI- HiPIPE, and a Super Frame Memory. The Super Frame Memory can display a ful color moving image sequence at a rate of 60 fps on a CRT monitor at a resolution of 2048 by 2048 pixels. Workstations, interconnected through an Ethernet, are used to control these units, and SHD image data can be easily transfered among the units. NOVI- HiPIPE has a frame memory which can display SHD still images on a color monitor, therefore, one processed frame can be directly displayed. We are developing SHD image processing algorithms and parallel processing methodologies using this system.

Multidimensional signal processing has recently been attracting attention in various fields, and has been studied theoretically. TV receives using 3-D (3-Dimensional: horizontal, vertical and temporal) processing, such as IDTV (ImproveD TV), are already available. In addition, television systems with high quality video and mostly with wide-aspect ratio are being studied worldwide. All the proposed systems adopt 3-D signal processing. 3-D processing can fully utilize the transmitted signal, and can take full advantage of the available bandwidth. This results in improved picture quality. This paper reviews the 3-D signal processing used in IDTV and EDTV (EnhanceD TV) in Japan. Video signals are analyzed in the 3-D frequency domain, and 3-D filter design is also studied.