This review presents research topics and results on digital signal processing in the last twenty years in Japan. The main parts of the review consist of design and analysis of multidimensional digital filters, multiple-valued logic circuits and number systems for signal processing, and general purpose signal processors.

The advantages of a neuro-chip architecture based on a DRAM are demonstrated through a discussion of the general issuse regarding a memory based neuro-chip architecture and a comparison with a chip based on an SRAM. The performance of both chips is compared assuming digital operation, a 1.5-V supply voltage, a 106-synapse neural network capability, and a 0.5-µm CMOS design rule. The use of a one-transistor DRAM cell array for the storage of synapse weights results in a chip 55% smaller than an SRAM based chip with the same 8-Mbit memory capacity and the same number of processing elements. No additional operations for refreshing the DRAM cell array are necessary during the processing of the neural networks. This is because all the synapse weights in the array are transferred to the processing elements during the processing and the DRAM cells in the array are automatically refreshed when they are selected. The precharge operation of the DRAM cell array degrades the processing speed, however a processing speed of 1.37 GCPS is expected for the DRAM based chip. That speed is comparable to the 1.71 GCPS for the SRAM based chip with the same 256 parallel-processing elements. A DRAM cell array has the additional advantage of lower power dissipation in this specific usage for the neuro-chip. The dynamic operation of the DRAM cell array results in a 10% lower operating power dissipation than a chip using an SRAM cell array at the same processing speed of 1.37 GCPS. That lower operating power dissipation enables a DRAM based chip to run on a 1.5-V dry cell for longer under intermittent daily use even though the SRAM cell array has little power dissipation in data-holding mode.

To realize next-generation high performance ULSI processors, it is a very important issue to reduce the critical delay path which is determined by a cascade chain of basic gates. To design highly parallel digital operation circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the non-linear digital system. On the other hand, the use of the linear concept in the digital system seems to be very attractive because analytical methods can be utilized. To meet the requirement, we propose a new design method of highly parallel linear digital circuits for unary operations using the concept of a cycle and a tree. In the linear digital circuit design, the analytical method can be developed using a representation matrix, so that the search procedure for optimal locally computable circuits becomes very simple. The evaluations demonstrate the usefulness of the circuit design algorithm.

The test pattern generation for sequential circuits is more difficult than that for combinational circuits due to the presence of memory elements. Therefore we proposed a method for synthesizing sequential circuits with testability in the level of state transition table. The state transition table is augmented by adding extra two inputs so that it possesses a distinguishing sequence, a synchronizing sequence, and transfer sequences of short length. In this case the checking sequence which do a complete verification of the circuit can be test pattern. The checking sequence have been impractical due to the longer checking sequence required. However, in this paper, we have discussed the condition to reduce the length of checking sequence, then by using suitable state assignment codes sequential circuits with much shorter checking sequences can be realized. A heuristic algorithm of the state assignment which reduce the length of checking sequence is proposed and the algorithm and reduced checking sequence are presented with simple example. The state assignment is very simple with the state matrix which represents the state transition. Furthermore some experimental results of automated synthesis for the MCNC Logic Synthesis Workshop finite state machine benchmark set have shown that the state assignment procedure is efficient for reducing checking sequences.

We Propose an integrated design and test assistance method for pipelined processors. Our approach generates behavioral-level test environments for pipeline control mechanisms from a machine-readable specification. It includes automatic generation of test programs and behavioral descriptions. Verification can be done by applying logic simulation to both the designers' descriptions and the behavioral descriptions, and then comparing the results. We have implemented an experimental system that enumerates all hazard patterns--instruction patterns that cause pipeline hazards--from the specifications, and generates the test programs and the behavioral descriptions for the pipeline controllers. The test programs cover all of the hazard patterns. The behavioral descriptions can manipulate any instruction stream. Experimental results for several RISC processors show that actual hazard patterns are too numerous to be easily enumerated by hand. Using workstations, our system can generate the test programs that cover all of the patterns, taking a few minutes. Results suggest that the system can be used to evaluate pipeline design.

This paper presents a simple numerical method for calculating the stationary transmission and reflection characteristics of a variety of nonlinear Fably-Perot resonators. In nonlinear media, Maxwell's equations are directly solved by using a numerical integration of complex variables. The input-output characteristics of the Kerr-like nonlinear film without reflection mirrors and with multilayer mirrors have been calculated to demonstrate the usefulness and versatility of the proposed method and to find out resonator configurations exhibiting optical bistability at low incident-power levels. The effects of saturation in the nonlinear permittivity on the input-output characteristics have also been investigated. It has been found that a single nonlinear film with oblique incidence exhibits optical bistability without using reflection mirrors even if the refractive index of the film is low. This offers a simple method for measuring third-order nonlinearities of optical materials.

This paper briefly considers future broadcasting technologies, including digital television as a system for the near future and three-dimensional television as a part of a system to be developed rather later. However, due to limitations of space, this paper discusses only video technologies in detail. First, the status of bit reduction technologies for digital television is described and then satellite digital broadcasting and terrestrial digital broadcasting are also discussed. The authors stress the necessity of the further development of digital video compression technologies. Later, we discuss three-dimensional television, we describe requirements for the service and the present status of the technologies. And last, the paper considers the future prospects for a three-dimensional television service.

This paper presents a hardware architecture design methodology for hidden markov model based recognition systems. With the aim of realizing more advanced and user-friendly systems, an effective architecture has been studied not only for decoding, but also learning to make it possible for the system to adapt itself to the user. Considering real-time decoding and the efficient learning procedures, a bi-directional ring array processor is proposed, that can handle various kinds of data and perform a large number of computations efficiently using parallel processing. With the array architecture, HMM sub-algorithms, the forward-backward and Baum-Welch algorithms for learning and the Viterbi algorithm for decoding, can be performed in a highly parallel manner. The indispensable HMM implementation techniques of scaling, smoothing, and estimation for multiple observations can be also carried out in the array without disturbing the regularity of parallel processing. Based on the array processor, we propose the configuration of a system that can realize all HMM processes including vector quantization. This paper also describes that a high PE utilization efficiency of about 70% to 90% can be achieved for a practical left-to-right type HMMs.

The performance of analog circuits is strongly influenced by their layout. Performance specifications are usually translated into physical constraints such as symmetry, common orientation, and distance constraints among certain components. Automatic digital layout tools can be adopted and modified to deal with the imposed performance constraints on the analog layout. The selection and modifications of algorithms to handle the analog constraints became the area of research in analog layout systems. The existing systems are characterized by the use of stochastic optimization techniques based placement, grid based or channel routers, and lack of compaction. In this paper, algorithms for analog circuit placement, routing, and compaction are presented. The proposed algorithms consider the analog oriented constraints, which are important from an analog layout point of view, and reduce the computation cost. The placement algorithm is based on a force directed method and consists of two main phases, each of which includes a tuning procedure. In the first phase, we solve a set of simultaneous linear equations, based upon the attractive forces. These attractive forces represent the interconnection topology of given blocks and some specified constraints. Symmetry constraint is considered throughout the tuning procedure. In the second phase, block overlap resulting from the first phase is resolved iteratively, where each iteration is followed by the symmetry tuning procedure. Routing is performed using a line expansion based gridless router. Routing constraints are taken into account and several routing priorities are imposed on the nets. The compactor part employs a constraint graph based algorithm while considering the analog symmetry constraints. The algorithms are implemented and integrated within an analog layout design system. An experimental result for an OP AMP provided by MCNC benchmark is shown to demonstrate the performance of the algorithms.

Switched-current (SI) is a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. In this paper, new switched-current (SI) mirrors using OTAs (operational transconductance amplifiers) are proposed. These circuits are less sensitive to clock-feedthrough noise than conventional SI mirrors by virtue of linear I-V/V-I transformations. In addition, the current gain of the proposed mirror is electronically tunable. Not only inverting mirrors but also noninverting mirrors can be realized by this method.

Oversampled analog-to-digital (A/D) converters based on sigma-delta (ΣΔ) modulation are attractive for VLSI implementation because they are especially tolertant of circuit nonidealities and component mismatch. Oversampled ΣΔ modulator has some points which must be improved. Some of these problems are based on the small input signal and the integrator leak. In this paper,ΣΔ A/D converter having a dither circuit to improve the linearity and the compensation technique of the integer leak are presented. By the simulation, the most suitable dither to improve the linearity of the modulator is obtained as follows: the amplitude is 1/150 of input signal maximum amplitude, the frequency is 4-times of the signal-band. Using the compensation circuit of the integrator leak, 72 dB of dynamic range is obtained when op-amp gain is 30 dB.

Behavior modeling of objects is critical in object-oriented design. In particular, it is essential to preserve integrity constraints on object behavior in application environments where objects of various classes dynamically interact with each other. In order to provide a stable design technique, a behavior model using the notion of the life cycle schema of a class is proposed. To model the aspect of behavioral abstraction of objects, the notion of schema refinement together with a diagrammatic representation technique is also defined. In this framework, a formalization of behavior constraints on objects which interact with each other is proposed together with its graphical representation. Verification rules of consistency of behavior constraints are also discussed. In order to perform certain functions, several partner objects of the same or different classes should collaborate establishing client-server relationships. The contract of a class is defined as a collection of responsibilities of a server class to a client class where each responsibility is specified in the form of the script. To achieve a high degree of systems integrity, a procedure to derive scripts from behavior constraints on collaborating partners is developed. It is also critical to evenly distribute responsibilities to partner objects. A delegation is placing a whole or a part of responsibilities of an object in charge of other objects. Based on the design principle delegation along the aggregation hierarchy,' a unified design approach to delegation that enables to reorganize scripts in constraints preserving way is proposed.

The approximation of the gain characteristics of linear phase FIR digital filters is reduced to the approximation by cosine polynomials. Therefore we can easily obtain an optimum solution under the LMS of Chebyshev error criterion. However the optimum solution does not always meet practical specifications, especially in the case where the gain is specified strictly at some angular frequencies. On the other hand in such a case, it is known that interpolation technique can be suitably applied for the approximation mentioned above. However, in this case, we encounter another difficulty in the approximation caused by interpolation. In order to overcome the above difficulty, this paper proposes a new method utilizing both of the interpolation and LMS techniques. Some parameters included in approximating functions are used to satisfy prescribed interpolating conditions and the other parameters are used to minimize the approximation error under the LMS criterion. In addition, interpolation technique is extended to include the case in which also higher derivatives are taken into interpolation conditions to make smooth interpolation. An example is shown to illustrate the effectiveness of the proposed method.

This paper proposes a superposed SSMA (Spread Spectrum Multiple Access)-QPSK (Quadrature Phase Shift Keying) signal transmission scheme over high speed QPSK signals to achieve higher frequency utilization efficiency and to facilitate lower power transmitters for SSMA-QPSK signal transmission. Experimental results show that the proposed scheme which employs the coding-rate of one-half FEC (Forward Error Correction) and a newly proposed co-channel interference cancellation scheme for SSMA-QPSK signals can transmit twenty SSMA-QPSK channels simultaneously over a nonlinearly amplified high speed QPSK signal transmission channel and achieve as ten times SSMA channels transmission as that without co-channel interference cancellation when the SSMA-QPSK signal power to the high speed QPSK signal power ratio equals -30dB. Moreover, cancellation feasibility generation of the interference signals replica through practical hardware implementation is clarified.

An idea of optimal output permutation of multiple-valued sum-of-products expressions is presented. The sum-of-products involve the TSUM operator on the MIN of window literal functions. Some bounds on the maximum number of implicants needed to cover an output permuted function are clarified. One-variable output permuted functions require at most p1 implicants in their minimal sum-of-products expressions, where p is the radix. Two-variable functions with radix between three and six are analyzed. Some speculations of maximum number of the implicants could be established for functions with higher radix and more than 2-variables. The result of computer simulation shows that we can have a saving of approximately 15% on the average using permuting output values. Moreover, we demonstrate the output permutation based on the output density as a simpler method. For the permutation, some speculation is shown and the computer simulation shows a saving of approximately 10% on the average.

This paper presents Bi-CMOS current-mode multiple valued logic circuit with 1.5 V supply voltage. This circuit is composed of current mirror, threshold detector and current source. This circuit has advantages such as high accuracy, high speed, high density and low supply voltage. So, it is possible to realize high-radix multiple valued logic circuit. As an other application of the proposed circuit, a processing unit of fuzzy inference is given. This circuit operates with high speed and high accuracy. The circuit simulation of the proposed circuit has been performed using SPICE2 program.

This paper presents an optimal constraint graph generation algorithm for graph-based one-dimensional layout compaction. The first published algorithm for this problem was the shadow-propagation algorithm. However, without sophisticated implementation of a shadow-front, complexity of the algorithm could fall into O(n2), where n is the number of layout objects. Although our algorithm, called the enhanced plane-sweep based graph generation algorithm, is an extension of the shadow-propagation algorithm, such a drawback is resolved by introducing an enhanced plane-sweep technique. The algorithm maintains multiple shadow-fronts simultaneously by storing them in a work-list called previous-boundary. Since a balanced search tree is selected for implementation of the worklist, total complexity of the algorithm is O(n log n) which is optimal. Experimental results show that the enhanced plane-sweep based graph generation algorithm runs in almost linear time with respect to the number of layout objects and is faster than the perpendicular plane-sweep algorithm which is also optimal in terms of time complexity.

In this paper, we propose an algorithm of O(|V|min{k,|V|,|A|}|A|) time complexity for finding all k-edge-connected components of a given digraph D=(V,A) and a positive integer k. When D is symmetric, incorporating a preprocessing reduces this time complexity to O(|A|+|V|2+|V|min{k,|V|}min{k|V|,|A|}), which is at most O(|A|+k2|V|2).

A model of a single neuron with chaotic dynamics is implemented with current-mode circuit design technique. The existence of chaotic dynamics in the circuit is demonstrated by simulation with SPICE3. The proposed circuit is suitable for implementing a chaotic neural network composed of such neuron models on a VLSI chip.

We propose a design method for a two-channel perfect reconstruction FIR filter banks employing linear-phase filters. This type of filter bank is especially important in splitting image signals into frequency bands for subband image cording. Because in such an application, it is necessary to use the combination of linear-phase filters and symmetric image signal, namely linear phase signal to avoid the increase in image size caused by filtering. In this paper, first we summarize the design conditions for two-channel filter banks. Next, we show that the design problem is reduced to a very simple linear equation, by using a half-band filter as a lowpass filter. Also the proposed method is available to lead filters with fewer complexity, which enable us to use simple arithmetic operations. For subband coding, the property is important because it reduces hardware complexity.