This paper proposes novel optical path accommodation design algorithms for networks wherein the number of wavelengths multiplexed into a fiber is restricted. This algorithm optimizes both optical path route and wavelength assignment in VWP/WP networks. It minimizes optical path cross-connect (OPXC) system scale in terms of incoming/outgoing fiber port numbers. A comparison in terms of required OPXC system scale between the WP and VWP schemes is demonstrated for the first time.

This paper describes, from a system architectural viewpoint, how knowledge-based technologies have been utilized in developing EXLOG (an LSI circuit synthesis system) and SOFTEX (a software synthesis system) inside the authors' projects. Although the system architectures for EXLOG and SOFTEX started from the same production systems, consisting of transformation rules in the middle of the 1980's, both branched off in different directions in the 1990's. Based on experiences with EXLOG and SOFTEX, the differences between LSI and software design models are discussed, and the future directions are indicated for the knowledge-based design system architectures.

High speed GaAs ICs (Integrated Circutis) using FETs (Field Effect Transistors) are reported. As the fabricating techniques, ion implantation processes for both 0.5 µm and 0.2 µm gate FETs using W/Al refractory metal and 0.2 µm recessed gate process with MBE grown epitaxial wafers are shown. These fabrication processes are selected depending on the circuit speed and the integration level. The outline of the circuit design and the examples of ICs, which are developed for 10 Gb/s optical communication systems, are also shown with the obtained characteristics.

A high efficiency and low voltage operation GaAs power amplifier module has been developed for the application to 1.5 GHz Japanese digital cellular phones. This paper summarizes the design method to increase efficiency and to reduce adjacent channel leakage power. Operated at a low drain bias voltage of 4.6 V, the power amplifier module delivers an output power of 1.5 W with 46% power-added efficiency and -52 dBs adjacent channel leakage power.

This paper presents an improved neural network for channel assignment problems in cellular mobile communication systems in the new co-channel interference model. Sengoku et al. first proposed the neural network for the same problem, which can find solutions only in small size cellular systems with up to 40 cells in our simulations. For the practical use in the next generation's cellular systems, the performance of our improved neural network is verified by large size cellular systems with up to 500 cells. The newly defined energy function and the motion equation with two heuristics in our neural network achieve the goal of finding optimum or near-optimum solutions in a nearly constant time.

To support high bit rate and high quality indoor radio communication systems, we have to solve intersymbol interference (ISI) problem caused by frequency-selective fading. Recently multi-carrier modulation technique is considered to be one of the effective methods for this problem. In this paper we propose Partial Frequency ARQ (Automatic Repeat reQuest) system which can achieve effective ARQ scheme for multi-carrier packet communication. This system operates partial retransmission of erroneous power faded packets, and it is superior to the traditional ARQ systems. Furthermore two different protocols are examined for this system: Static Carrier Assignment (SCA) and Dynamic Carrier Assignment (DCA). By computer simulation we found that DCA method can achieve better performance than SCA in terms of both throughput and packet transmission delay.

In this paper, we propose two parallel processing methods for multidimensional (MD) sampling lattice alteration. The use of our proposed methods enables us to alter the sampling lattice of a given MD signal sequence in parallel without any redundancy caused by up- and down-sampling, even if the alteration is rational and non-separable. Our proposed methods are provided by extending two conventional block processing techniques for FIR filtering: the overlap-add method and the overlap-save method. In these proposed methods, firstly a given signal sequence is segmented into some blocks, secondly sampling lattice alteration is implemented for each block data individually, and finally the results are fitted together to obtain the output sequence which is identical to the sequence obtained from the direct sampling lattice alteration. Besides, we provide their efficient implementation: the DFT-domain approach, and give some comments on the computational complexity in order to show the effectiveness of our proposed methods.

A signal-to-noise enhancer with a bandwidth that is six times as wide as that of the conventional type is presented. A new circuit construction, the combination of two MSSW filters which have the same insertion loss in the broadband and two 90 hybrids, is effective to remarkably extend the bandwidth. The enhancement of the enhancer amounts to 20 dB in the operating frequency range of 1.9 GHz150 MHz in 0 to 60 degrees centigrade. This enhancer has accomplished FM threshold extension because the S/N is improved by 1 to 7 dB below the C/N of 9 dB. It was demonstrated that this new enhancer is effective for noise reduction in practical DBS reception.

The most creative tasks in synthesizing pipelined data paths executing software descriptions are determinations of latency and stage of pipeline, operation scheduling and hardware allocation. They are interrelated closely and depend on each other; thus finding its optimal solution has been a hard problem so far. By using simulated annealing methodology, these three tasks can be formulated as a three dimensional placement problem of operations in stage, time step and functional units space. This paper presents an efficient method based on simulated annealing to provide excellent solutions to the problem of not only the determinations of latency and stage of pipeline, operation scheduling and hardware allocation simultaneously, but also the pipelined data path synthesis under the constraints of performance or hardware cost. It is able to find a near optimal latency and stage of pipeline, an operation schedule and a hardware allocation in a reasonable time, while effectively exploring the existing tradeoffs in the design space.

This paper describes a system that can enchance the speech quality degradation due to severe band limitation during speech transmission. We have already proposed a spectrum widening method that utilizes aliasing in sampling rate conversion and digital filtering for spectrum shaping. This paper proposes a new method that offers improved performance in terms of the spectrum distortion characteristics. Implementation procedures are clarified, and its performance is discussed. The proposed method can effectively enhance speech quality.

A novel method is presented for designing discrete coeffcient FIR linear phase filters using Hopfield neural networks. The proposed method is based on the minimization of the energy function of Hopfield neural networks. In the proposed method, the optimal solution for each filter gain factor is first searched for, then the optimal filter gain factor is selected. Therefore, a good solution in the specified criterion can be obtained. The feature of the proposed method is that it can be used to design FIR linear phase filters with different criterions simultaneously. A design example is presented to demonstrate The effectiveness of the proposed method.

This paper proposes a modified normalized LMS algorithm based on a long-term average of the reference input signal power. The reference input signal power for normalization is estimated by using two leaky integrators with a short and a long time constants. Computer simulation results compare the performance of the proposed algorithm with some previosuly proposed adaptive-step algorithms. The proposed algorithm converges faster than the conventional adaptive-step algorithms. Almost 30dB of the ERLE (Echo Return Loss Enhancement), which is comparable to the conventional algorithms, is achieved in noisy environments.

In this paper, we discuss design of quadrature mirror filter (QMF) banks using digital allpass networks in the frequency domain. In the QMF banks composed of a parallel connection of two allpass networks, both aliasing error and amplitude distortion are always completely canceled. Therefore, we only need to design the analysis filters and eliminate phase distortion of the overall transfer function. We consider design of the QMF banks in two cases where phase responses of the filters are repuired or not required. In the case where the phase responses are not required, the design problem can be reduced to design of phase difference of two allpass networks. In the case where the phase responses are required, we present a procedure for designing the QMF banks with both equiripple magnitude and phase responses.

A bottleneck identification methodology is proposed for the performance-oriented design of shared-bus multiprocessors, which are composed of several major subsystems (e.g. off-chip cache, bus, memory, I/O). A subsystem with the longest access time per instruction is the one that limits processor performance and creates a bottleneck to the system. The methodology also facilitates further refined analysis on the access time of the bottleneck subsystem to help identify the causes of the bottleneck. Example performance model of a particular shared-bus multiprocessor architecture with separate address bus and data bus is developed to illustrate the key idea of the bottleneck identification methodology. Accessing conflicts in subsystems and DMA transfers are also considered in the model.

The distributed measurement-based quasi-fixed frequency assignment (also known as quasi-static adaptive frequency assignment-QSAFA) methodology is a practical solution for frequency assignment in the emerging TDMA personal communications networks (PCN/PCS). Five different QSAFA algorithms are studied in this paper under different interference threshold settings. It is found that a simple aggressive algorithm without using a threshold (LIA-Least Interference Algorithm) performs the best under the conditions studied. The performance of this algorithm is also justified by the theoretical proof presented at the end of this paper.

The investigation of device functions required from the systems point of view will be important for the development of the next generation of VLSI devices and systems. In this paper, a super pass transistor (SPT) model is presented as a quantum device candidate for future VLSI systems based on multiple-valued logic. A possible quantum device structure for the SPT model is also described, which employs the concepts of a lateral-resonant-tunneling quantum-dot transistor and a heterostructure field-effect transistor. Since it has the powerful capability of detecting multiple signal levels, the SPT will be useful for the implementation of highly compact multiple-valued VLSI systems. To exploit the functionality of the SPT, a super pass gate (SP-gate) corresponding to a single SPT is proposed as a multiple-valued universal logic module. The mathematical properties of the SP-gate are discussed. A design method for a multiple-valued SP-gate network is presented. An application of SP-gates to a multiple-valued image processing system is also demonstrated. The SP-gate network for the multiple-valued image processing system is evaluated in comparison with the corresponding NMOS implementation in terms of the number of transistors, interconnections and cascaded transistor stages. The size of a generalized series-parallel SP-gate network is also evaluated in comparison with a functionally equivalent multiple-valued series-parallel MOS pass transistor network. The results show that highly compact multiple-valued VLSI systems can be achieved if the SPT-model can be realized by an actual quantum device.

This paper proposes a human interface where a novel input method is used to substitute conventional input devices. It overcomes the deficiencies of physical devices, as it is based on image processing techniques. The proposed interface is composed of three parts: extraction of a person's handshape from a digitized image, detection of its fingertip, and interpretation by a software application. First, images of a pointing hand are digitized to obtain a sequence of monochrome frames. In each frame the hand is isolated from the background by means of gray-level slicing; with threshold values calculated dynamically by the combination of movement detection and histogram analysis. The advantage of this approach is that the system adapts itself to any user and compensates any changes in the illumination, while in conventional methods the threshold values are previously defined or markers have to be attached to the hand in order to give reference points. Second, once the hand is isolated, fingertip coordinates are extracted by scanning the image. Third, the coordinates are inputted to an application interface. Overall, as the algorithms are simple and only monochrome images are used, the amount of processing is kept low, making this system suitable to real-time processing without needing expensive hardware.

In the final stages of VLSI testing, improved quality VLSI testing is an important subject for ensuring reliability in the forwarded VLSI market. On the other hand, developments in high integration technology have resulted in an increased number of functional blocks in VLSI devices and an increased number of gates for each terminal. Consequently, it has become more difficult to improve the quality of VLSI tests. We have developed a new test method in addition to conventional testing methods intended for improving the test coverage in VLSI tests. This new test method analyzes the relationship between IDDq (Quiescent Power Supply Current) of DUT and DUT failure by applying the concept of the toggle rate. Accordingly, in this paper we report that the results of IDDq testing confirm a correlation with defect level.

An optimum design scheme for logical network topologies on a Flexible Multi-QoS Logical ATM Network, named Full-Net, is proposed. Full-Net offers high-quality Virtual-Path (VP) networks and controls end-to-end QoS only at the VP-network's access points. To develop the optimum network topology for multimedia traffic in a single ATM network, a logically con figured Virtual Channel Handler (VCH) interconnection network is associated with each QoS class. Many logical networks can be mapped at the same time on the same network, because mapping is independent of the network's physical implementation. To achieve an optimum design scheme for logical networks, the number of disjoint routes is introduced as the parameter used to optimize logical network topology. The number of disjoint routes is chosen so as to maximize total network efficiency. The optimum number of disjoint routes depends on the required QoS, VC-traffic characteristics, and traffic demand. By choosing the relevant cost characteristics, the network operator can easily maximize network efficiency and provide customers with the QoS they request at minimum cost. The proposed optimum multi-QoS network design scheme on a Full-Net architecture is an efficient solution to implementing multi-QoS control in an ATM network.

This paper presents the concept of k-FR circuits. The controllability of such a circuit is high due to its special structure. It is shown that all stuck-at faults and stuck-open faults in a k-FR circuit can be detected and located by k(k1)1 test vectors under the highly observable condition which assumes the output of every gate to be observable. k is usually two or three. This paper also presents an algorithm for converting an arbitrary combinational circuit into a k-FR circuit. A k-FR circuit is easy to test when using technologies such as the electron-beam probing, the current measurement, or the CrossCheck testability solution.