AlGaAs/GaAs power HBTs for digital cellular phones have been developed. A three-dimensional thermal analysis taking the local-temperature dependence of the collector current into account was applied to the thermal design of the HBTs. The HBTs were fabricated using the hetero-guardring fully selfaligned transistor technique. The HBT with 220µm2 60 emitters produced a 31.7 dBm CW-output power and 46% poweradded efficiency with an adjacent channel leakage power of -49 dBc at the 50kHz offset bands for a 948 MHz π/4-shifted QPSK modulated signal at a low collector-emitter voltage of 3V. Through comparison with the conventional GaAs power FETs, it has been shown that AlGaAs/GaAs power HBTs have a great advantage in reducing the chip size.

A new global method for constructing a C2 piecewise quartic polynomial curve is presented. The coefficient matrix of equations which must be solved to construct the curve is tridiagonal. The joining points of adjacent curve segments are the given data points. The constructed curve reproduces exactly a polynomial of degree four or less. The results of experiments to test the efficiency of the new method are also shown.

Fundamental microwave key devices used in achieving compact mobile/portable telephones (raidio units) are discussed. The historical development flow of the systems and radio units are introduced, with respect to the 800-/900-MHz and 1.5-GHz Japanese cellular radio systems. The design concept of the developed radio units is briefly described. Tehnical requirements for RF circuits are reviewed and the developed key devices are practically applied to the circuits. Key factors in the requirements are also shown. Finally. future trends fro the key devices are surveyed from the stand point of achieving a smaller and more light weight pocket radio unit.

This paper proposes a design technique for 3-D non-separable QMF banks with Face-Centered Cubic Sampling (FCCS) and Body-Centered Cubic Sampling (BCCS). In the proposed technique, 2-D McClellan transformation is applied to a suitably designed 2-D prototype QMF to obtain 3-D QMFs. The design examples given in this paper demonstrate advantages of the proposed method.

In the business systems design learning environment, there may be more than one solution to any given problem. For instance, the data model will be different depending on each learner's perspective. Accordingly, group learning systems are very effective in this domain. We have developed CAMELOT (Collaborative and Multimedia Environment for Learners on Teams) [18] using the Nominal Group Technique for group problem solving. In this paper, the basic framework of the collaborative learning system and the effectiveness of collaborative learning in designing the Data Model are described. By using CAMELOT, each learner learns how to analyze through case studies and how to cooperate with his or her group in problem solving. Learners come to a deeper understanding from using CAMELOT than from studying independently because they are enabled to reach better solutions through discussion, tips from other learners, and examination of one another's works.

Discussed here is progress achieved in the development of video codec LSIs.First, the amount of computation for various standards, and signal handling capability (throughput) and power dissipation for video codec LSIs are described. Then, general technologies for improving throughtput are briefly summarized. The paper also reviews three approaches (i.e., video signal processor, building block and monolithic codes) for implementing video codes standards. The second half of the paper discusses various high-throughput technologies developed for programmable Video Signal Processor (VSP) LSIs. A number of VSP LSIs are introduced, including the world's first programmable VSP, developed in February 1987 and a monolithic codec ship, built in February 1993 that is sufficient in itself for the construction of a video encoder for encoding full-CIF data at 30 frames per second. Technologies for reduction of power dissipation while keeping maintaining throughput are also discussed.

This paper presents a combinatiorial characterization of broadcast authentication in which a transmitter broadcasts v messages e1(s), , ev(s) to authenticate a source state s to all n receivers so that any k receivers cannot cheat any other receivers, where ei is a key. Suppose that each receiver has l keys. First, we prove that k < l if v < n. Then we show an upper bound of n such that n v(v - 1)/l(l - 1) for k = l - 1 and n /+ for k < l - 1. Further, a scheme for k = 1 - 1 which meets the upper bound is presented by using a BIBD and a scheme for k < l - 1 such than n = / is presented by using a Steiner system. Some other efficient schemes are also presented.

A speedup of Lenstra's Elliptic Curve Method of factorization is presented. The speedup works for integers of the form N = PQ2, where P is a prime sufficiently smaller than Q. The result is of interest to cryptographers, since integers with secret factorization of this form are being used in digital signatures. The algorithm makes use of what we call Jacobi signatures. We believe these to be of independent interest.

A microphone array system with multi-stage processing for speech enhancement is presented in this paper. Two beamformers with uniform directional patterns, one aimed at the target source and the other at the interfering sources, convert the multi-channel inputs into two data sequences. A novel microphone array structure with a small aperture has been designed to obtain the dual beamformers. The outputs of the two beam-formers are then presented to a post-processing stage to further improve the quality and intelligibility of the speech signal. The post-processing stage can be selected from one of three different algorithms that are presented, which are suitable for different acoustic environments. Applications for such a system include hands-free telephony, teleconferencing and also special situations where speech signals must be picked up in an extremely noisy acoustic environment in which the microphones are hidden (e.g. in a forensic covert recording system).

This paper presents implicit representation of binary decision diagrams (implicit BDDs) as a new effecient data structure for Boolean functions. A well-known method of representing graphs by binary decision diagrams (BDDs) is applied to BDDs themselves. Namely, it is a BDD representation of BDDs. Regularity in the structure of BDDs representing certain Boolean functions contributes to significant reduction in size of the resulting implicit BDD repersentation. Since the implicit BDDs also provide canonical forms for Boolean functions, the equivalence of the two implicit BDD forms is decided in time proportional to the representation size. We also show an algorithm to maniqulate Boolean functions on this implicit data structure.

To realize high-speed computations in a residue number system (RNS), an implementation method for residue arithmetic circuits using signed-digit (SD) number representation is proposed. Integers mp = (2p-1) known as Mersenne numbers are used as moduli, so that modulo mp addition can be performed by an end-around-carry SD adder and the addition time is independent of the word length of operands. Using a binary modulo mp SD adder tree, the modulo mp multiplication can be performed in a time proportional to log2p.

We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering a current flowing from input node to output node through gate capacitances, the accuracy is improved significantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experiments. A improved circuit simulation technique for short-circuit power dissipation is presented. Since this formula calculate the short-circuit power dissipation accurately and quickly, it will be applied to power sensible CAD tools.

The dynamic channel assignment (DCA) strategy proposed here uses information on the mobile station speed and direction of motion to reduce the number of forced call terminations and channel changes in micro cellular systems. This SMD (speed and moving direction) strategy is compared with the main DCA strategies by simulating a one-dimensional service area covering a road on which there are high-speed mobile stations (HSMSs) and low-speed mobile stations (LSMSs).The simulation results show that the SMD strategy has the best performance in terms of forced call termination and channel change. The performance difference between the SMD strategy and the other DCA strategies increases as cell size decreases and as HSMS speed increases. While the SMD strategy does not yield the best total call blocking rate, its total carried load is the best when cells are small and HSMS speed is high. Also, the SMD performance improves when the HSMS offered load is small and the LSMS offered load is large. Although the SMD strategy requires information on the speed and direction of each mobile station and it increases call blockings somewhat, it reduces the number of forced call terminations and channel changes considerably, which is important in micro cellular systems.

A new methodology for simulation-based CMOS process design has been proposed, using a Hierarchical Response Surface Method (HRSM) and an efficient experimental calibration. The design methodology has been verified using a 0.4 micron CMOS process. The proposed HRSM achieved a 60% reduction of process and device design cost in comparison with those of conventional TCAD. The procedure was performed in conjunction with an experimental calibration technique to provide a reliable threshold voltage prediction including process variation effects. The total CPU cost was 200 hr. on SUN SPARC 10 and the error of the predicted threshold voltage was less than 0.02 V.

This letter presents a new design method for approximate inverse systems using all-pass networks. The efficacy of approximate inverse systems for input and parameter estimation of nonminimum phase systems is well recognized. in the previous methods, only time domain design of FIR (finite impulse response) type approximate inverse systems were considered. Here, we demonstrate that IIR (infinite impulse response) type approximate inverse systems outperform the previous methods. A nonlinear optimization technique is adopted for designing the proposed system in the frequency domain. Numerical examples are also presented to show the effectiveness of the proposed method.

This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-µm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5-0.2µm scaled CMOS devices.

This paper reviews an application of optical techniques to Microwave Signal Processing (MSP), such as frequency multiplexing using external optical modulators (EOMs), and microwave frequency add-drop multiplexing and mixing using semisconductor optical amplifiers (SOAs), as well as microwave phase control in the optical domain. The cascaded EOM links can be applied to microwave and millimeter-wave signal distribution networks. The add-drop links using SOAs can make it possible to realize a compact and cost-effective radio repeater for radio signal distribution. The several SOA mixing link configurations are also described.

In a (k,n) threshold digital signature scheme, k out of n signers must cooperate to issue a signature. In this paper, we show an efncient (k,n) threshold EIGamal type digital signature scheme with no trusted center. We first present a variant of EIGamal type digital signature scheme which requires only a linear combination of two shared secrets when applied to the (k,n)-threshold scenario. More precisely, it is a variant of Digital Signature Standard (DSS) which was recommended by the U.S. National Institute ofStandard and Technology (NIST). We consider that it is meaningful to develop an efficient (k,n)-threshold digital signature scheme for DSS. The proposed (k,n)-threshold digital signature scheme is proved to be as secure as the proposed variant of DSS against chosen message attack.

Computer viruses, hackers, intrusions and ther computer crimes have recently become a serious security problem in information systems. Digital signatures are useful to defend against these threats, especially against computer viruses. This is because a modification of a file can be detected by checking the consistency of the originai file with its accompanying digital signature. But an executable program might have been infected with the viruses before the signature was created. In this case, the infection cannot be detected by signature verification and the origin of the infection cannot be specified either. In this paper, we propose a signature scheme in which one can sign right after the creation of an executable program. That is, when a user compiles a source program, the compiler automatically creates both the executable program and its signature. Thus viruses cannot infect the executable programs without detection. Moreover, we can specify the creator of contaminated executable programs. In our signature scheme, a signature is created from a set of secret integers stored in a compiler, which is calculated from a compiler-maker's secret key. Each compiler is possessed by only one user and it is used only when a secret value is fed into it. In this way a signature of an executable program and the compiler-owner are linked to each other. Despite these measures, an executable program could run abnormally because of an infection in prepro-cessing step, e.g. an infection of library files or included files. An infection of these files is detected by ordinary digital signatures. The proposed signature scheme together with digital signature against infection in the preprocessing step enables us to specify the origin of the infection. The name of the signature creator is not necessary for detecting an infection. So, an owner's public value is not searched in our scheme, and only a public value of a compiler-maker is required for signature verification. Furthermore, no one can use a compiler owned by another to create a proper signature.

A design method of 2-D lattice digital filter using the Genetic Algorithm (GA) is proposed. By using the GA. 2-D all-pole lattice filter with the cascade connection of transversal (all-zoro) filter is designed directly from a given desired frequency responce.