FIR digital filters composed of parallel multiple subfilters are proposed. A binary expression of an input signal is decomposed into multiple shorter words, which drive the subfilters having different length. The output error is evaluated by mean squared and maximum spectra. A fast algorithm is also proposed to determine optimal filter lengths and coefficients of subfilters. Many examples confirm that the proposed filters generate smaller output errors than conventional filters under the condition of specified number of multiplications and additions in filter operations. Further, multiplier and adder structures (MAS) to perform the operations of the proposed filters are also presented. The number of gates used in the proposed MAS and its critical path are estimated. The effectiveness of the proposed MAS is confirmed.

This paper describes key technologies for implementing ATM internode signalling. The reliability of a multimedia handling network can be improved by setting multiple virtual paths(VPs)between two nodes and setting signalling links over each internode VP. A software structure appropriate for handling the signalling protocol(MTP3b)within this framework is proposed. We also propose a cost-effective and reliable way to set a signalling route between a node and the service control point(SCP), based on the associate mode structure. Evaluation by implementing a node system shows that it requires only 15% more dynamic program steps for one sending/receiving sequence of the VP signalling than the existing method for circuit-related information. Thus, we could attain highly reliable and cost-effective signalling for ATM multimedia networks.

The tape deformation due to such particles as wear debris and dust in the head/tape contact region is one of the main causes of the signal quality deterioration in magnetic tape devices. Thus it is significant to make clear the tape deformation due to a particle for realizing higher recording densities. This paper investigates the tape deformation profile generated by a particle through an interferometric experiment and a simulation using a point loaded tape model. A rather good agreement between them is obtained, thereby the simulation is verified appropriate to estimate the tape deformation due to a particle. This paper also describes the relationship between the spacing loss and the particle height, considering the tape deformation profile obtained from the simulation. In addition, the influence of the particle height on the width of the tape deformed area is estimated, which can make a basis of the design of error correction code.

VP Network Designer, a software tool that automates the tasks involved in the transaction of service orders in VP leased line services, is introduced here in this paper. The tool is composed of two functions: VP Design Explorer which, given a request for VP establishment, determines a disjoint backup and target VP routes to support fault tolerance under VP-APS scheme; Network Resource Administrator which provides data administering functions, useful in maintaining a clear insight into the state of the network. The paper focuses on the implementation of VP Design Explorer. A scheme, proposed as disjoint VP routes search, is used to evaluate a pair of VP routes that guarantee duct level independence. The scheme is based on an integer programming modeling approach, and is proved to be effective for evaluating disjoint paths in a hierarchical network. VP Design Explorer is equipped with an additional feature where, under conditions of resource shortage, it presents a set of additional resources that are necessary to satisfy VP demand, together with the VP routes that become possible by the additions. Formulation of the problem is attained through an extension of the disjoint VP routes search scheme. A prototype of VP Network Designer is presented and its performance tested using computer simulations. The tool is found to achieve a computational time performance in the order of seconds and minutes, for evaluating disjoint VP routes search problems under real life ATM network conditions.

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (1. 5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 µW, it has a sufficient input range, whereas conventional Wang's OTA needs 703 µW to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.

If the fiber dispersion of soliton transmission line is optimized, the amplifiers output power becomes almost constant for different amplifier spacing and pulse width. Numerical simulations indicate the optimal dispersion can be determined, as the ratio of amplifier spacing to dispersion length is about 0. 8 for uniform dispersion line.

In the literatures [5] and [10], a systematic discussion is presented with respect to the optimum interpolation of multi-dimensional signals. However, the measures of error in these literatures are defined only in each limited block separately. Further, in these literatures, most of the discussion is limited to theoretical treatment and, for example, realization of higher order linear phase FIR filter bank is not considered. In this paper, we will present the optimum interpolation functions minimizing various measures of approximation error simultaneously. Firstly, we outline necessary formulation for the time-limited interpolation functions ψm(t) (m=0,1,. . . ,M-1) realizing the optimum approximation in each limited block separately, where m are the index numbers for analysis filters. Secondly, under some assumptions, we will present analytic or piece-wise analytic interpolation functions φm(t) minimizing various measures of approximation error defined at discrete time samples n=0, 1, 2,. . . . In this discussion, φm(n) are equal to ψm(n) n=0, 1, 2,. . . . Since ψm(t) are time-limited, φm(n) vanish outside of finite set of n. Hence, in designing discrete filter bank, one can use FIR filters if one wants to realize discrete synthesis filters which impulse responses are φm(n). Finally, we will present one-dimensional linear phase M channel FIR filter bank with high attenuation characteristic in each stop band. In this design, we adopt the cosine-sine modulation initially, and then, use the iterative approximation based on the reciprocal property.

In this letter, a realization of current-mode active filter using current followers as active element is described. We show the constructions of second-order lowpass, highpass and bandpass filters. The high-order filters can be realized by a cascade connection of these second filters. As examples, the second-order lowpass and highpass filters are designed for frequency of 5 MHz. The effectiveness of the proposed method is demonstrated through SPICE simulation.

This paper examines the design considerations for an opamp to be used in a low-power consumption LCD driver IC: (1) slew rate enhancement suitable for a rail-to-rail input stage; (2) improved phase compensation with reduced compensation capacitance; and (3) limitation of instantaneous current consumption. The experimental results support our opamp design approach and indicate the feasibility of a 10 µA quiescent current opamp.

This correspondence reports novel computationally efficient algorithms for multiplication of bicomplex numbers, which belong to hypercomplex numbers. The proposed algorithms require less number of real multiplications than existing methods. Furthermore, they give more effective implementation when applied to constant coefficient digital filters.

In Asiacrypt '96, Bleichenbacher et al. showed the upper limit of the efficiency of one-time digital signature scheme using a directed graph of tree structure as its base. They also claimed that there exists more effective signature scheme on general directed graphs, and showed an example of a method to construct more effective signature schemes as a witness. Unfortunately, their example does not achieve the efficiency as they claimed. This paper shows the upper limit of the efficiency of the signature scheme on general directed graphs by showing no signature scheme is more effective than the optimal signature scheme on trees (or forests). Further, we introduce another signature scheme named pseudo k-time signature scheme. This signature scheme allows signers to sign k-time which is no less efficient than the one time signature scheme.

This paper presents two types of two-dimensional (2-D) adaptive beamforming algorithm which have high rate of convergence. One is a linearly constrained minimum variance (LCMV) beamforming algorithm which minimizes the average output power of a beamformer, and the other is a generalized sidelobe canceler (GSC) algorithm which generalizes the notion of a linear constraint by using the multiple linear constraints. In both algorithms, we apply a 2-D lattice filter to an adaptive filtering since the 2-D lattice filter provides excellent properties compared to a transversal filter. In order to evaluate the validity of the algorithm, we perform computer simulations. The experimental results show that the algorithm can reject interference signals while maintaining the direction of desired signal, and can improve convergent performance.

The addition chain (A-chain) and addition-subtraction chain (AS-chain) are efficient tools to calculate power Me (or multiplication eM), where integere is fixed andM is variable. Since the optimization problem to find the shortest A (or AS)-chain is NP-hard, many algorithms to get a sub-optimal A (or AS)-chain in polynomial time are proposed. In this paper, a window method for the AS-chain and an extended window method for the A-chain and AS-chain are proposed and their performances are theoretically evaluated by applying the theory of the optimal variable-to-fixed length code, i. e. , Tunstall code, in data compression. It is shown by theory and simulation that the proposed algorithms are more efficient than other algorithms in practical cases in addition to the asymptotic case.

A new broadband space diversity (B-SD) combining method, which is a key technique in the growth of digital microwave radio system, is proposed. In this B-SD combining method, two received signals, whose bandwidths are 280 MHz, are combined. To develop this combining method, an optimum control algorithm is developed that monitors power levels of all primary carriers and controls the endless phase shifter so that the higher level signal is decreased and the lower level signal is increased. This paper describes the proposed B-SD combining method which effectively operates over a wide bandwidth. Performance evaluations based on simulations and theoretical estimations are given. It is proven that this combining method offers the same performance obtained by the conventional narrowband SD combining method and can be applied to over 50% cases of the propagation paths observed in Japan. The suitability of the proposed combining method and the calculation methods adopted is demonstrated experimentally.

In this paper, a threshold voltage (VT) cancellation circuit for neuron-MOS (νMOS) analog circuits is described. By connecting the output terminal of this circuit with one of the input terminals of the νMOS transistor, cancellation ofVT is realized. The circuit has advantages of ground-referenced output and is insensitive to the fluctuation of bias and supply voltages. Second-order effects, such as the channel length modulation effect, the mobility reduction effect and device mismatch of the proposed circuit are analyzed in detail. Low-power and high-swing νMOS cascode current mirror is presented as an application. Performance of the proposed circuits is confirmed by HSPICE simulation with MOSIS 2. 0 µ p-well double-poly and double-metal CMOS device parameters.

An adaptive infinite impulse response (IIR) filter implemented using an allpass and a minimum phase system has an advantage of its poles converging to the poles of the unknown system when the input is a white signal. However, when the input signal is colored, convergence speed deteriorates considerably, even to the point of lack of convergence for certain colored signals. Furthermore with a colored input signal, there is no guarantee that the poles of the adaptive digital filter (ADF) will converge to the poles of the unknown system. In this paper we propose a method which uses a linear predictor filter to whiten the input signal so as to improve the convergence characteristic. Computer simulation results confirm the increase in convergence speed and the convergence of the poles of the ADF to the poles of the unknown system even when the input is a colored signal.

Fiat-Shamir's identification and signature scheme is efficient as well as provably secure, but it has a problem in that the transmitted information size and memory size cannot simultaneously be small. This paper proposes an identification and signature scheme which overcomes this problem. Our scheme is based on the difficulty of extracting theL-th roots modn (e. g.L=2 1020) when the factors ofnare unknown. We prove that the sequential version of our scheme is a zero knowledge interactive proof system and our parallel version reveals no transferable information if the factoring is difficult. The speed of our scheme's typical implementation is at least one order of magnitude faster than that of the RSA scheme and is relatively slow in comparison with that of the Fiat-Shamir scheme.

We propose a new method for verifying synchronous circuits using the Boyer-Moore Theorem Prover (BMTP) based on an efficient use of induction. The method contains two techniques. The one is the representation method of signals. Each signal is represented not as a waveform, but as a time parameterized function. The other is the mechanical transformation of the circuit description. A simple description of the logical connection of the components of a circuit is transformed into such a form that is not only acceptable as a definition of BMTP but also adequate for applying induction. We formalize the method and show that it realizes an efficient proof.

We present a new scheduling policy named Value-based Processor Allocation (VPA-k) for scheduling value-based transactions in a multiprocessor real-time database system. The value of a transaction represents the profit the transaction contributes to the system if it is completed before its deadline. Using VPA-k policy, the transactions with higher values are given higher priorities to execute first, while at most k percentage of the total processors are allocated to the urgent transactions dynamically. Through simulation experiments, VPA-k policy is shown to outperform other scheduling policies substantially in both maximizing the totally obtained values and minimizing the number of missed transactions.

A multiple signature scheme proposed in [1] is proved to be insecure.