This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s.

This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.

Digital Signal Processors with complex arithmetic capability (DSP-C) are useful for various applications. In this paper, we propose a method for the effective implementation of specific circuits with real coefficients on DSP-C. DSP-C has special hardware such as a complex multiplier so that a complex calculation can be performed with only one instruction. First, we show that nodes with two real coefficient input branches can be implemented by complex multiplications. We apply this implementation to 2D circuits and transversal circuits with real coefficients. Next, we introduce a new computational mode (Advanced mode) and a new multiplier into PSI, a kind of DSP-C which has been proposed already, in order to process the circuits effectively. The effectiveness of the proposed method is shown by simulation in the last part.

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 hours, making this method 5 times more efficient than conventional methods

Multi-input floating gate differential amplifier (FGDA) is proposed which can perform any convolution operation with differential structure and feedback loop. All operations are in the voltage mode. Only one terminal is required for the negative feedback which can suppress distortions due to mismatches of active elements. Possible applications include intelligent image sensor, where fully parallel DCT operation can be performed. A prototype chip is fabricated which is functional. A preliminary test result is reported.

Lots of self-tuning control schemes have been proposed for tuning the parameters of control systems. Among them, pole-assignment schemes have been widely used for tuning the parameters of control systems with unknown time delays. They are usually classified into two methods, the implicit and the explicit methods according to how to identify the parameters. The latter has an advantage to design a control scheme by taking account of the stability margin and control performance. However, it involves a considerably computational burden to solve a Diophantine equation. A simple scheme is proposed in this paper, which can construct a multivariable self-tuning pole-assignment control system, while taking account of the stability margin and control performance without solving a Diophantine equation.

In this paper, we propose two methods of digital watermark for image signals based on the wavelet transform. We classify wavelet coefficients as insignificant or significant by using zerotree which is defined in the embedded zerotree wavelet (EZW) algorithm . In the first method, information data are embedded as watermark in the location of insignificant coefficients. In the second method, information data can be embedded by thresholding and modifying significant coefficients at the coarser scales in perceptually important spectral components of image signals. Information data are detected by using the position of zerotree's root and the threshold value after the wavelet decomposition of an image in which data hide. It is shown from the numerical experiments that the proposed methods can extract the watermark from images that have degraded through several common signal and geometric processing procedures.

This paper proposes the first provably secure multi-signature schemes under the random oracle model. The security of our schemes can be proven in the sense of concrete security in Ref. [13]. The proposed schemes are efficient if the random oracle is replaced by practical hash functions. The essential techniques in our proof of security are the optimal reduction from breaking the corresponding identification to breaking signatures (ID Reduction Technique), and the hierarchical heavy row lemmas used in the concrete reduction from solving the primitive problem to breaking the identification scheme.

We consider an algorithm for finding all solutions in order to clarify all the stable equilibrium points of a hysteresis neural network. The algorithm includes sign test, linear programming test and a novel subroutine that divides the solution domain efficiently. Using the hysteresis network, we synthesize an associative memory whose cross connection parameters are trinalized. Applying the algorithm to the case where 10 desired memories are stored into 77 cells network, we have clarified all the solutions. Especially, we have confirmed that no spurious memory exists as the trinalization is suitable.

The security of the ElGamal-type signature scheme is based on the difficulty of solving a discrete logarithm problem. If a random value that is introduced in the signing procedure is small, then the time for generating signature can be reduced. This strategy is particularly advantageous when a signer uses a smart card. In this paper, we show that the secret key can be computed efficiently if the random value is less than O(q) where q is the order of the generator.

This paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Data path allocation is achieved by a controllability and observability balance allocation technique which is based on testability analysis at register-transfer level. Scheduling, on other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. Contrary to other works in which the scheduling and allocation tasks are performed independently, our approach integrates scheduling and allocation by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. Additionally, since sequential loops are widely recognized to make a design hard-to-test, a complete (functional and topological) loop analysis is performed at register-transfer level in order to avoid loop creation during the integrated test synthesis process. With a variety of synthesis benchmarks, experimental results show clearly the advantages of the proposed algorithm.

This letter examines outline measures of strength against the differential and linear cryptanalysis. These measures are useful to estimate the number of rounds giving an immune iterated cipher. This letter reports that the outline measures of strength are useful to relatively estimate the strength of generalized feistel ciphers.

This paper is concerned with radio resource allocation in multiple-chip-rate (MCR) DS/CDMA systems accommodating multimedia services with different information rates and quality requirements. Considering both power spectral density (PSD) over a radio frequency (RF) band and the effect of RF input filtering on the receiver in MCR-DS/CDMA systems, criteria for capacity estimation are presented and the characteristics of co-channel interference between subsystems are investigated. System performance in MCR-DS/CDMA systems is strongly affected by radio resource assignment. A minimum power-increment-based resource assignment scheme for an efficient resource assignment scheme is proposed herein. The performance of this scheme is compared with that of a random-based resource assignment scheme in terms of blocking probability and normalized throughput. The minimum power-increment-based resource assignment scheme yields a better performance than the random-based resource assignment scheme for multimedia services.

In ordinary digital signature schemes, anyone can verify signatures with signer's public key. However it is not necessary for anyone to be convinced a justification of signer's dishonorable message such as a bill. It is enough for a receiver only to convince outsiders of signature's justification if the signer does not execute a contract. On the other hand there exist messages such as official documents which will be first treated as limited verifier signatures but after a few years as ordinary digital signatures. We will propose a limited verifier signature scheme based on Horster-Michels-Petersen's authenticated encryption schemes, and show that our limited verifier signature scheme is more efficient than Chaum-Antwerpen undeniable signature schemes in a certain situation. And we will propose a convertible limited verifier signature scheme based on our limited verifier signature scheme, and show that our convertible limited verifier signature scheme is more efficient than Boyar-Chaum-Damg rd-Pedersen convertible undeniable signature schemes in a certain situation.

In this paper, we propose a method, called PORT-D, for optimizing CMOS logic circuits to reduce the average power dissipation. PORT-D is an extensional method of PORT. While PORT reduces the average power dissipation under the zero delay model, PORT-D reduces the average power dissipation by taking into account of the gate delay. In PORT-D, the average power dissipation is estimated by the revised BDD traversal method. The revised BDD traversal method calculates switching activity of gate output by constructing OBDD's without representing switching condition of a gate output. PORT-D modifies the circuit in order to reduce the average power dissipation, where transformations which reduce the average power dissipation are found by using permissible functions. Experimental results for benchmark circuits show PORT-D reduces the average power dissipation more than the number of transistors. Furthermore, we modify PORT-D to have high power reduction capability. In the revised method, named PORT-MIX, a mixture strategy of PORT and PORT-D is implemented. Experimental results show PORT-MIX has higher power reduction capability and higher area optimization capability than PORT-D.

This paper proposes an intelligent and autonomous radio resource management scheme for a multi-layered cellular system with different assigned bandwidths to achieve flexible and high capacity wireless communication systems under any traffic conditions, especially under nonuniform traffic conditions. In the proposed system, terminals with lower mobility are connected to the wideband microcell systems to achieve higher system capacity, and terminals with higher mobility are connected to the narrowband macrocell systems to reduce intercell hand-off frequency. To flexibly cope with variations of traffic conditions, radio spectrum is adaptively and autonomously shared by both systems, and its control is conducted by each microcell base station. Moreover, at the existence of nonuniform traffic conditions , the proposed system introduces downlink power control for the microcells and graceful degradation thereby achieving high system capacity even under such extraordinary traffic situations . Computer simulation confirms that the proposed scheme can achieve lower blocking probability than the centralized scheme especially under nonuniform traffic conditions.

In this paper, we propose a new register transfer level (RT level) testability analysis method. Controllability and observability measures are defined for signal vectors based on the numbers of values they can take. The control part and the datapath part are automatically identified in the given RT level model and distinctive analysis methods are applied. We also describe a DFT point selection method based on our testability measures. In a experiment on a signal processing circuit whose gate count is 7690 including 578 FFs, almost the same fault coverage is achieved with fewer scan FFs than a conventional method based on gate level testability analysis.

Providing various assistances for design modifications on HDL source codes is important for design reuse and quick design cycle in VLSI CAD. Program slicing is a software-engineering technique for analyzing, abstracting, and transforming programs. We show algorithms for extracting/removing behaviors of specified signals in VHDL descriptions. We also describe a VHDL slicing system and show experimental results of efficiently extracting components from VHDL descriptions.

For the improvement of software quality and productivity, the author aims at realizing a software development environment to develop software through utilizing the merits of group work. Since networking is necessary for collaborative software development, he has developed a software distributed development environment for collaborative software development. In this environment, discussions about software design are held through a communication network, and the contents of discussions are recorded as software design decisions and decision rationale. One feature of this environment is that the contents of discussions can be recorded in on-line real time and reused without reconstructing the information recorded through this environment. This paper clarifies the essential conditions for actualizing this environment and proposes an information structure model for recording the contents of discussions that actualizes the above-mentioned feature. The effectiveness of the proposed model is proved through an example of its application to software design discussions.

This paper presents a new routing method that takes into account neighboring-wire-capacitance (inter-layer and intra-layer) constraints. Intermediate routing (IR) assigns each H/V wire segment to the detailed routing (DR) grid using global routing (GR) results, considering the neighboring-wire constraints (NWC) for critical nets. In DR, the results of IR for constrained nets and their neighboring wires are preserved, and violations that occur in IR are corrected. A simple method for setting NWC that satisfy the initial wire capacitance given in a set-wire-load (SWL) file is also presented. The routing method enables more accurate delay evaluation by considering inter-wire capacitance before DR, and avoids long and costly turnaround in deepsubmicron layout design. Experimental results using MCNC benchmark test data shows that the errors between the maximum delay from IR and that from DR for each net were less than 5% for long (long delay) nets.