This paper proposes a new method for recovering the original signals from their linear mixtures observed by the same number of sensors. It is performed by identifying the linear transform from the sources to the sensors, only using the sensor signals. The only assumption of the source signals is basically the fact that they are statistically mutually independent. In order to perform the 'blind' identification, some time-correlational information in the observed signals are utilized. The most important feature of the method is that the full information of available time-correlation data (second-order statistics) is evaluated, as opposed to the conventional methods. To this end, an information-theoretic cost function is introduced, and the unknown linear transform is found by minimizing it. The propsed method gives a more stable solution than the conventional methods.

This paper deals with an orthogonal functional expansion of a non-linear stochastic functional of a stationary binary sequence taking 1 with equal probability. Several mathematical formulas, such as multi-variate orthogonal polynomials, recurrence formula and generating function, are given in explicit form. A simple example of orthogonal functional expansion and stationary random seqence generated by the stationary binary sequence are discussed.

The multiple registration schemes (MRSs) proposed here are classified into 3 cases by combining five registration schemes which are power up registration scheme (PURS), power down registration scheme (PDRS), zone based registration scheme (ZBRS), distance based registration scheme (DBRS), and implicit registration scheme (IRS) as follows: the first is MRS1 which covers PURS, PDRS, and ZBRS; the second is MRS2 which covers PURS, PDRS, and DBRS; the third is MRS3 which covers PURS, PDRS, IRS, and DBRS. The three proposed schemes are compared each other by analyzing their combined signaling traffic of paging and registration with considering various parameters of a mobile station behavior (unencumbered call duration, power up and down rate, velocity, etc.). Also, we derive allowable location areas from which the optimal location area is obtained. Numerical results show that MRS3 yields better performance than ZBRS, DBRS, MRS1, and MRS2 in most cases of a mobile station behavior, and it has an advantage of distributing the load of signaling traffic into every cell, which is important in personal communication system.

This paper reviews analog LSI design issues for optical transmission applications; covering ultra-high-speed transmission over 10 Gb/s, multi-Gb/s systems, optical interconnection systems, and optical access. In the future system development, further advancements in not only optical device technology but also LSI technology are eagerly required. More and more sophisticated circuit design techniques are needed to lower power and operation voltage, increase integration, eliminate external elements and adjustments.

In the adaptive lattice estimation process, it is well known that the convergence speed of the successive stage is affected by the estimation errors of reflection coefficients in its preceding stages. In this paper, we propose block estimation methods of two-dimensional (2-D) adaptive lattice filter. The convergence speed of the proposed algorithm is significantly enhanced by improving the adaptive performance of preceding stages. Furthermore, this process can be simply realized. The modeling of 2-D AR field and texture image are demonstrated through computer simulations.

This paper proposes a parallel word alignment procedure for m Binary with 1 Complement Insertion (mBlC) or Differential m Binary with l Mark Insertion (DmBlM) line code. In the proposed procedure for mBlC line code, the word alignment circuit searches (m+1) bit pairs in parallel for complementary relationships. A Signal Flow Graph Model for the parallel word alignment procedure is also proposed, and its performance attributes are numerically analyzed. The attributes are compared with those of the conventional bit-by-bit procedure, and it is shown that the proposed procedure displays superior performance in terms of False-Alignment Probability and Maximum Average Aligning Time. The proposed procedure is suitable for high speed optical data links, because it can be easily implemented using a parallel signal processor operating at a clock rate equal to 1/(m+1) times the mBlC line rate.

This paper presents an efficient optimal block terminal assignment algorithm based on the integer programming for a data path synthesis. The problem is to assign buses to commutable terminals on functional units such that the number of buses is minimum, when the scheduling and allocation of operations and registers have been done. Three methods are used in the algorithm to decrease the amount of computation.

The performance of synchronous VLSI system is limited by the speed of the global clock which is further constrained by the clock skew. Self-timed design technique, based on the Muller model, improves performance by eliminating the global clock. In order to prevent hazard, a self-timed system should satisfy certain assumptions and timing constraints, therefore special cells are required. The novel Self-timed Cell Library is designed for 1.2µm CMOS technology which contains Muller C-elements, DCVSL circuits, latches and delay elements. It is very useful because: (1) It avoids any possible violations of the assumptions and timing constraints since all cells are custom designed; (2) It provides a fast and reliable model for self-timed system verification using either SPICE simulator or Verilog simulator; (3) It is flexible since it is compatible with an existing Standard Cell Library. In this paper, the library is described. Moreover, the simulated and measured cell characteristics are compared. Using the library, two [18] [81] matrix multipliers employing (1) DCVSL technique, and (2) micropipeline technique have been implemented as design examples and the results are compared. In addition, this paper also demonstrates the benefits of custom-layouted C-elements and a new way to realize delay element for micropipeline. The last but not least, two new HCCs are also proposed.

In this paper, we discuss on accuracy of power dissipation medels for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with power consumption of actual VLSI chips. To evaluate the accuracy of several kinds of power dissipation models in chip-level, block-level and gate-lebel etc., we have been (i) Measuring power consumtion of actual microprocessors, (ii) Estimating power consumption with several kinds of power dissipation models, and (iii) Comparing (i) with (ii). The experimental results show as follows: (1) Power estimation at gate level is accurate enough. (2) Estimating power of a clock tree independently makes estimation more accurate. (3) Area of each functional block is a good approximation of load capacitance of the block.

In this paper, we give a concrete example of a 10-bit video rate ADC and introduce the effect of top-down design methodology with analog-HDL from the viewpoint of utilization techniques. First, we explain that analog top-down design methodology can improve chip performance by optimizing the architecture. Next, we concretely discuss the importance of modeling and verification. Verification of the full system does not require extracting all the information for each block at the transistor level in detail. The flexible verification method that we propose can provide good and fast full chip verification. We think analog top-down disign methodology will become increasingly more important from now on because "system-on-chip" requires one chip mixed-signal system LSIs.

This paper proposes a synthesis method to obtain speed-independent asynchronous circuits directly from signal transition graph (STG) specifications with single cycle signals which can be non-persistent and have free-choice operations. The resulting circuits are implemented with basic gates and asynchronous latches, and operate correctly under finite but unbounded gate delays and the zero wire delay assumptions. The proposed method introduces 5 types of lock relations to implement a non-persistent STG. A non-persistent STG can be implemented if every non-persistent signal to a signal t is super-locked with t. The resulting circuits are optimized by extracting of literals, mapping onto asymmetric C-elements, etc. Experimental results show that the proposed synthesis method outperforms the existing synthesis systems such as SYN and SIS.

Signal Transition Graphs (STG's) are Petri nets, which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on an Occurrence net (OCN) and its prefix, called an unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating sub state space of a given STG using the structural properties of OCN.

This paper describes the design and evaluation of fully scannable embedded memory arrays. A memory array, such as a register file, is made scannable by adding a small auxiliary circuit including a counter and multiplexers. Plural memory arrays can be chained into a single scan path along with ordinary flip-flops. Detailed configuration and implementation of the scannable CMOS and bipolar LCML register file macros are discussed. The overhead ratio of the CMOS register file macro with 16-word by 16-bit results in an 8.6% transistor count and a 6.4% die area. The access time overhaead is 7.8% and the set-up time increases by about 50ps. Bipolar LCML register file macros have been applied to gate array LSIs which have successfully achieved average stuck-at fault coverage of 99.2%.

We apply a novel methodology, based on statecharts, to the design of large scale asynchronous systems. The design is specified at multiple levels, simulated, animated, and compiled into synthesizable VHDL code by using the ExpressV-HDL CAD tool. We add a validation sub-system to chech correct operation. ExpressV-HDL is originally synchronous, but we employ it for asynchronous design by avoiding any design dependence on the clock, and simulating with fast clock and on-line delays. The tool is demonstrated through a simple FSM. The synthesized synchronous circuit can be converted into an asynchronous one. Some results of a post-synthesis conversion example are given.

In this paper we describe the implementation of complex architectures using a general design approach for two-phase asynchronous systems. This fundamental approach, called Event Controlled Systems, can be used to widely extend the utility of two phase systems. We describe solutions that we have developed that dramatically improve the performance of static and dynamic-logic asynchronous pipelines, and briefly describe a complex microprocessor designed using ECS.

Many efforts are currently underway to design wideband mobile communication systems. In this letter, we clarify the received signal level characteristics for wideband mobile radio channels in line-of-sight (LOS) microcells. We conduct several urban-area field experiments to measure the received signal levels for various receiver bandwidths from 300 kHz to 30 MHz and the power delay profile. The experimental results show that the fading depth of the received signal decreases as the normalized rms delay spread, defined as the product of receiver bandwidth and rms delay spread, increases. These results are useful in designing wideband microcell systems for urban areas.

Built-in self-test (BIST) has been applied to test an analog to digital converter (ADC) and a digital to analog converter (DAC) embedded in a DSP-core ASIC. The eight performance characteristics of the ADC and the DAC designed in accordance with the ITU-T recommendations are measured using the BIST. Three of the eight characteristics - the attenuation/frequency distortion, the variation of gain with input level, and the signal-to-total distortion - have been evaluated and the measured results have shown good agreement with measured results by conventional tests. In the BIST operation, the DSP-core generates input stimulus and analyzes output response by control of the self-test program, The sizes of the self-test program and coefficient data are 822 words of the IROM and 384 words of the data ROM, respectively. This area overhead is less than 0.5% of total chip area. Test-time by the BIST is reduced to approximately 3.2 seconds, which is one-tenth that of conventional testing. The mixed-signal DSP-core ASIC is testable with only logic test equipment, and as a result, test-cost - that is test investment and test-time - is reduced compared with conventional test methods.

The design and engineering of new network intelligence platforms to accommodate the ever-changing and growing demands of customers, presents rich market opportunities and challenges tempered by concerns arising from the problematic experiences of similar system and network developments. As the telecommunications industry evolves, customers are increasingly coming to expect the perception of instantaneous access to service providers together with transparency to network failures. System performance dictates that response times need to be minimised, sufficient redundant capacity installed in case of failure and controls embedded within the design to manage the exceptional situations (such as media stimulated events) that continually threaten network integrity. Network design based on a 'top-down,' 'end-to-end' methodology plays a fundamental role in delivering solutions that meet customers' performance needs. It is necessary to consider service scenario mixes, service demand, physical network topology, signalling message flows, the mapping of functional entities to physical components, and routing as part of the network design process to ensure that performance requirements are met. The use of 'what-if' design tools is particularly relevant as part of this process. A challenging task faces the System Designer with the often conflicting goals of good performance and provision of service flexibility.

This paper discusses the development of a design tool which supports a process for constructing PVC-based, ATM networks. Because of mathematical complexities, a heuristic approach has been adopted to find an optimal network configuration. Through a GUI, users define a physical network, and PVC networks which are logically constructed within the physical network. Based on the defined network configurations and user traffic demand, the tool evaluates performance measures. In response to the results of the evaluation, network designers can modify the network configuration to improve the performance. With the aid of this tool, they can repeat this interactive process until the estimated performance measures meet a desired quality. The tool has been applied to the design of several private ATM networks which will be constructed in the near future. The response time of this design tool is so fast that wait time can be negligible.

A novel adder-free architecture for realizing a small-size π/4-shift QPSK signal generator IC is presented. In order to realize an adder function, analog current-mode addition is utilized instead of digital adders. Impulse responses of a roll-off filter are stored in a ROM as a Δ-Σ modulated one-bit data stream. This can greatly reduce the die size to 0.8mm 0.8mm while maintaining high modulation accuracy. The test chip was fabricated by using the standard 0.8µm CMOS technology, and the chip achieved 1.8% vector modulation error with a 2.7V power supply.