A novel cryptographic key assignment scheme for dynamic access control in a user hierarchy is presented. Based on Rabin's public key system and Chinese remainder theorem, each security class SCi is assigned a secret key Ki and some public parameters. In our scheme, a secret key is generated in a bottom-up manner so as to reduce the computation time for key generation and the storage size for public parameters. We also show that our proposed scheme is not only secure but also efficient.

Recently, two new efficient server-aided RSA secret computation protocols were proposed. They are efficient and can guard against some active attacks. In this letter, we propose two multi-round active attacks which can effectively reduce their security level even break them.

After analyzing the limitations of the traditional description of CMOS circuits at the gate level, this paper introduces the notions of switching and signal variables for describing the switching states of MOS transistors and signals in CMOS circuits, respectively. Two connection operations for describing the interaction between MOS transistors and signals and a new description for MOS circuits at the switch level are presented. This new description can be used to express the functional relationship between inputs and the output at the switch level. It can also be used to describe the circuit structure composed of MOS switches. The new description can be effectively used to design both CMOS circuits and nMOS pass transistor circuits.

In VLSI and printed wiring board design, routing process usually consists of two stages: the global routing and the detailed routing. The routability checking is to decide whether the global wires can be transformed into the detailed ones or not. In this paper, we propose two graphs, the capacity checking graph and the initial flow graph, for efficient routability checking in planar layouts.

We have previously proposed a scannable memory configuration which is useful in testing logic blocks around memory arrays. Although the configuration is supposed to be effective in testing the memory array itself by its frequent read/write access during the scan operation, it has not been theoretically shown what types of faults can be detected. In this paper, from a viewpoint of memory testing, we investigate the testability of the scannable memory configuration and propose a memory array test using the scan path. It is shown that we can detect (1) all stuck-at faults in memory cells, (2) all stuck-at faults in address decoders, (3) all stuck-at faults in read/write logic, (4) static, dynamic and 2-coupling faults between memory cells of adjacent words, and (5) static coupling faults between memory cells in the same word. The test can be accomplished simply by comparing scan-in data and scan-out data. The test vector is 20ms bit long, where m is the number of words of the memory array under test and s is the total scan path length.

We present here the Controlling Value Boolean Matching based on fault analysis. The problem is to match a Boolean function with don't cares on library cells under arbitrary input permutations and/or input-output phase assignments. Most of the library cells can be represented by tree structure circuits. The approach presented here is suitable for these structures and computes the Boolean matching better than the structural matching used in SIS. It can handle library cells with a general topology and reconvergent paths. The benchmark test shows that the Controlling Value Boolean Matching can be as facter as the structural matching used in SIS.

Signal flow determination of CMOS/VLSI digital circuits is a key issue for switch-level CAD tools such as timing and testability analysers, functional abstractors, ATPGs etc. and even some simulators. Signal flow determination is used to pre-process circuit MOS transistors in order to improve both the accuracy and the running time of these CAD tools. Existing algorithms can be classified into two main categories: the rule-based approach and the algorithm-based approach. However, both of them have several drawbacks. This paper presents an efficient algorithm based on a novel mixed algorithmic and rule based approach. Our algorithm overcomes most of the drawbacks of the pure algorithmic and rule based approaches. It is based on a set of "safe" topological rules rather than ad hoc or technology dependent ones, while the algorithmic aspect of our approach is based on a recursive Depth First Search (DFS). Due to the algorithmic aspect of our approach, some rules consider circuit global effects such as path informations. Our approach provides the advantages of the rule based one (i.e.: the flexibility and the adaptability toward the great variety of CMOS design styles) as well as the advantages of the algorithmic approach (i.e.: the fast processing time and the ability to consider circuits global effects). The result is that the software is very accurate since all the unidirectional and bidirectional transistors are correctly identified in all the pathological benchmarks reported in the literature.

This work is targeted to understand the operating principle of the feedback type echo canceller for use in an FM broadcasting receiver and to study its compensating features and the effects of the practical operating environment on its performance. The effects of the tap interval and the compensation performance in the presence of an echo with excess delay 0 - 15 µs are examined. The results show that the tap interval should be selected according to the observable bandwidth of the channel transfer function and the performance of a feedback type echo canceller has a wavelike curve with respect to the excess delay of the echo. To improve the performance of the feedback type echo canceller, an adaptive echo canceller operating with CM algorithm is proposed and examined with computer simulation. The results show that the compensation performance is improved.

Key technologies are presented for enhancing the reusability of software in communication switching node systems along with the results obtained from porting software between several types of node systems, including N-ISDN, B-ISDNs, and Intelligent Networks. A reusable software platform based on object-oriented designing and programming techniques has been established and mechanisms for reusing object classes has been developed. Analysis of the reusability showed that this platform can be applied to various types of communication systems and that an average of more than three quarters of a system's programs can be ported. By using our software reuse framework to develop software components, we were able to reduce the time needed to develop device management programs by about 30%. Furthermore, about 80% of these programs can be ported to other systems, so introducing this platform improves software programming productivity.

Recently, the spatio-temporal filter using linear analog Cellular Neural Network (CNN), called CNN filter array, has been proposed for the purpose of dynamic image processing. In this paper, we propose a design method of descrete-time cellular neural network filter which selectively extracts the particular moving object from other moving objects and noise. The CNN filter array forms a spatio-temporal filter by arranging cells with a same function. Each of these cells is a simple linear analog temporal filter whose input is the weighted sum of its neighborhood inputs and outputs and each cell corresponds to each pixel. The CNN filter is formed by new model of discrete time CNN, and the filter parameters are determined by applying backpropagation algorithm in place of the analytic method. Since the number of connections between neurons in the CNN-type filter is relatively few, the required computation in the learning phase is reasonable amount. Further, the output S/N ratio is improved by introducing nonlinear element. That is, if the ratio of output to imput is smaller than a certain value, the output signal is treated as a noise signal and ought to be rejected. Through some examples, it is shown that the target object is enhanced in the noisy environment.

This paper presents an event-driven approach to the timing verification of latch-synchronized systems. The proposed method performs critical path extraction and timing error detection at the same time, and extracts the critical path only if necessary. By doing so, the complexity of analysis is reduced and efficiency is greatly improved over the conventional approaches which detect timing errors after extracting the complete critical paths of the system. Experimental results show that, compared to the existing methods, it provides a more than 12-fold improvement in speed on the average for ISCAS benchmark circuits, and the relative efficiency of analysis improves as the circuit size grows.

Based on a new search strategy using circuit simulation and simulated annealing with local search, a design tool is proposed to automate design or tuning process for CMOS operational amplifiers. A special-purpose circuit simulator and some heuristics are used to accomplish the design within reasonable time. For arbitrary circuit topology and specifications, the discrete optimization of cost function is performed by global and local search. Through the comparision of design results and the design of a low-power high-speed CMOS operational amplifier usable in 10-b 25-MHz pipelined A/D converters, it has been demonstrated that this tool can be used for designing high-performance operational amplifiers with less design knowledge and effort.

It is indispensable to establish a multi-access protocol and resource management technique that can assure transmission quality and efficiently utilize the radio frequency spectrum for ATM-based wireless access systems. This paper proposes dynamic time-slot assignment schemes for the forward link from a user to a central station (CS): (1) the centralized assignment and release scheme (CAR), and (2) the centralized-assignment and autonomous-release scheme (CAAR). In the proposed schemes, a central station dynamically assigns time-slots based on traffic information obtained by monitoring the input traffic in each radio module (RM). In addition, forward protection is used to prevent false-release of assigned time-slots. Performance evaluations have been carried out by analysis as well as computer simulations. They show that the proposed schemes achieve good performance in delay, link stability, and utilization efficiency of radio resources with an optimized number of forward protection steps.

This paper presents a clock routing technique called Balanced-Mesh Method (BMM) which incorporates the advantages of two famous conventional-clock-routing techniques. One is the balanced-tree method (BTM) where the clock net is routed as a tree so that the delay times of clock signal are balanced, and the other is the fixed-mesh method (FMM) where the clock net is routed as a fixed mesh driven by a large buffer. In BMM, the clock net is routed as a set of relatively small meshes of interconnects driven by relatively small buffers. Each mesh covers an area called a Mesh-Routing Region (MR) in which its delay and skew can be suppressed within a certain range. These small meshes are connected by a balanced tree with the chip clock source as its root. To implement BMM, we developed an MR-partitioning program that partitions the circuit into MR's according to a set of pre-determined constraints on the number of flip-flops and the area in each MR, and a clock-global-routing program that provides each mesh routing and the tree routing connecting meshes. We applied BMM to the design of an MPEG2-encoder LSI and achieved a skew of 210ps. In addition, the experimental results show BMM yields the lowest power dissipation compared to conventional methods.

A new cost function based on multi-band decomposition of the estimation error and application of a different step-size for each band is used in connection with the least-mean-square criterion to improve the fidelity of estimates as compared to those obtained with conventional least-mean-square adaptive algorithms. The basic new idea is to trade off time and frequency resolutions of the adaptive algorithm along the frequency domain by using different step-sizes in the analysis of distinct frequencies in accordance with the frequency-localized statistical behavior of the imput signal. The mathematical background for a stochatic approach to the multi-band decomposition-based scheme is presented and algorithms with fixed and variable step-sizes are derived. Computer experiments compare the performance of multiband and conventional least-mean-square methods when applied to system identification.

Block delay caused by using fast Fourier transform (FFT), and computational complexity in sampling rate conversion system are considered in this paper. The relationship between the number of block delays and the computational complexity is investigated. The proposed method can avoid the redundant operations of sampling rate conversion completely and moreover provide a good trade-off between the number of block delays and the computational complexity. As a result, ti is shown that with the proposed method, the sampling rate conversion can be realized more efficiently under a small number of block delays.

This paper proposes a nonlinear signal processing by using a three layered network which is trained with self-organized clustering and supervised learning. The network consists of three layers, i.e., self-organized layer, an evaluation layer and an output layer. Since the evaluation layer is designed as a simple perceptron network and the output layer is designed as a fixed weight linear node, the training complexity is the same as a conventional one consisting of self-organized clustering and a simple perceptron network. In other words, quite high speed training can be realized. Generally speaking, since the data range is arbitrary large in signal procession, the network shoulk cover this range and output a value as accurately as possible. However, it may be hard for only a node in the network to output these data. Instead of this mechanism, if this dynamic range is covered by using several nodes, the complexity of each node is reduced and the associated range is also limited. This results on the higher performance of the network than conventional RBFs. This paper introduces a new non-linear spectrum estimation which consists of LPC analysis and RBF network. It is shown that accuracy spectrum envelopes can be obtained since a new RBF network can estimate some nonlinearities in a speech production.

The TLS method is an unbiased estimator for solving the overdetermined set of linear equations when errors occur in all data. However it doesn't show robustness while the errors have a heavy tailed pdf. In this letter we derive a robust method of TLS (ROTLS) based on the characteristics of TLS solution, where the performance of ROTLS is verified by applying it to the system identification problem.

A new multiple-valued current-mode (MVCM) integrated circuit using a switched current-source control technique is proposed for a 1.5 V-supply high-speed arithmetic circuit with low-power dissipation. The use of a differential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In the proposed DLC using a switched current control technique, the static power dissipation can be greatly reduced because current sources in non-active circuit blocks are turned off. Since the gate of each current source is directly controlled by using a multiphase clock whose technique has been already used in dynamic circuit design, no additional transistors are required for currentsource control. As a typical example of arithmetic circuits, a new 1.5 V-supply 5454-bit multiplier based on a 0.8µm standard CMOS technology is also designed. Its performance is about 1.3 times faster than that of a binary fastest multiplier under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the proposed MVCM integrated circuit.

A new method is proposed for estimating a single complex sinusoid and its parameters (frequency and amplitude) from measurements corrupted by white noise. This method is called the ECKF-SVD method, which is derived by applying an extended complex Kalman filter (ECKF) to a nonlinear stochastic system whose state variables consist of the AR coefficient (a function of frequency) and a sample of the original signal. Proof of the stability is given in the case of a single sinusoid. Simulations demonstrate that the proposed ECKF-SVD method is effective for estimating a single complex sinusoid and its frequency under a low signal-to-noise ratio (SNR). In addition, the amplitude estimation by means of the ECKF-SVD method is also discussed.