Discussed here is reduction of power dissipation for multi-media LSIs. First, both active power dissipation Pat and stand-by power dissipation Pst for both CMOS LSIs and GaAs LSIs are summarized. Then, general technologies for reducing Pat are discussed. Also reviewed are a wide variety of approaches (i.e., parallel and pipeline schemes, Chen's fast DCT algorithms, hierarchical search scheme for motion vectors, etc.) for reduction of Pat. The last part of the paper focuses on reduction of Pst. Reducing both Pat and Pst requires that both throughput and active chip areas be either maintained or improved.

This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1: n2 for the N-type MOS cascode circuit and n2: 1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a VT level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits aer confirmed by SPICE simulation with MOSIS 1.2µm CMOS process parameters.

New interference cancellation technique using time division reference signal is proposed for optical synchronous code-division multiple-access (CDMA) systems with modified prime sequence codes. In the proposed system one user in each group is not allowed to access the network at each time, and this unallowable user's channel is used as a reference signal for other users in the same group at the time. The performance of the proposed system using an avalanche photodiode (APD) is analyzed where the Gaussian approximation of the APD output is employed and the effects of APD noise, thermal noise, and interference for the receiver are included. The proposed cancellation techniqus is shown to be effective to improve the bit error probability performance and to alleviate the error floor when the number of users and the received optical power are not appreciably small.

A matched filter (Mf) based on analog filter technology for DS-CDMA mobile radio is presented. An experimental one-chip LSI of AMF is developed for measuring various areas of performance such as power consumption, cut-off frequency, and linearity. The measurements show that power consumption is only 110mW at a voltage supply of 3V and an operational clock frequency of 25 MHz. We implemented a RAKE combiner using experimental AMF LSI and measured the bit error rate (BER) performance of DS-CDMA signal transmission in a multipath fading environment.

This paper is devoted to a new design method for infinite impulse response approximate inverse system of a nonminimum phase system. The design is carried out such that the convolution of the nonminimum phase polynomial and its approximate inverse system can be represented by an approximately linear phase all-pass filter. A method for estimating the time delay and order of an approximate inverse system is also presented. Using infinite impulse response approximate inverse systems better accuracy is achieved with reduced computational complexity. Numerical examples are included to show the effectiveness of the proposed method.

We present an extended quarter-plane lattice model for generating two-dimensional (2-D) autoregressive fields. This work is a generalization of the extended lattice filter of diagonal form (ELDF) developed by Ertuzun et al. The proposed model represents a wider class of 2-D AR fields than conventional lattice models. Several examples are presented to demonstrate the applicability of the proposed model. Furthermore, the proposed structure is compared with other conventional lattice filters based on the computation of their entropy values.

We study individual carrier traps in a GaAs/AlxGa1-xAs heterostructure by observing random telegraph signals. A narrow channel, which is formed in a split gate device, is shifted by independently controlling the voltage applied to each part of the split gate. RTSs can be observed only when the traps are close to the channel and the energy levels of the traps are within a few kBT of the Fermi level. This type of measurement reveals the locations and the energy distributions of the traps. We also discuss the situation in which two trap levels are at the Fermi level simultaneously. In this condition the two RTSs do not occur at the same time, but they do interact with each other. This implies that there is an electrostatic interaction between the two trappings.

As IC fabrication technology enters a deepsubmicron region with device feature sizes <0.35µm, interconnect becomes the most dominant factor in design of high-speed Application Specific Integrated Circuits (ASICs). This paper proposes a novel methodology for automated data-path synthesis of such circuits and outlines algorithms to support it. In contrast to other approaches, we formulate interconnect area/delay optimizations as high-level synthesis transformations and use them during the synthesis to minimize the impact of wiring on circuit characteristics. Experiments with FIR filter implementations show that such formulation jointly with on the fly" module generation and performance-driven floorplanning provides more than a 30% reduction in wiring delay for deep sub-micron designs.

An efficient algorithm is proposed for finding all solutions of piecewise-linear resistive circuits The algorithm is based on the idea of "contraction" of the solution domain using a sign test. The proposed algorithm is efficient because many large super-regions containing no solution are eliminated in early steps.

In this paper partial response signalling and trellis coded modulation are considered together to improve bandwidth efficiency and error performance for M-QAM and denoted as Modified/Quadrature Partial Response-Trellis Coded Modulation (M/QPR-TCM) and two new non-catastrophic schemes M/6QPR-TCM and M/9QPR-TCM are introduced for 4QAM. In colored noise with correlation coefficient less than zero, the proposed schemes perform better than in AWGN case. Another interesting result is that when the combined system is used on a Rician fading channel, the bit error probability upper bounds of the proposed systems are better than their counterparts the 4QAM-TCM systems with 2 and 4 states, respectively, for SNR values greater than a threshold, which have the best error performance in the literature.

An approach to design for testability using register-transfer level (RTL) partial scan selection is described. We define an RTL circuit model which enables efficient description in an electronic system design automation (ESDA) tool and testability analysis which leads to effective partial scan selection for RTL design including data path circuits and control circuits such as state machines. We also introduced a method of partial scan selection at RTL which selects critical registers and state machines based on RTL testability analysis. DFT techniques using gate level testability measures have been studied and concluded that they are not successful in achieving high fault coverage [15]. However, we started this work for the following reasons, 1) In sequential ATPG procedure, more than two memory elements belonging to a functional units such as registers and state machines are often required to be justified at a time. At RTL, state machines and registers are explicitly described and recognized as functional units while gate level memory elements are scattered over the circuit. 2) As discussed in [6], if the circuit is modified so that the test sequence which causes state transition between initial and final states of sequential ATPG can be easily obtained, ATPG results can be also improved. Complex state machines can be identified at RTL. According to the experimental results, our gate level DFT achieves high fault coverage comparable with the previously published most successful DFT methods, and DFT at RTL resulted in higher fault coverage than gate level DFT at much shorter CPU time.

In order to apply formal design verification, it is necessary to describe formally and correctly the specification of the circuit under verification. Especially when we apply conventional OBDD-based logic comparison method for verifying combinational circuits, another correct" logic circuits or Boolean formulae must be given as the specification. It is desired to develop an efficient automatic design verification method which interprets specification that can be described easier. This paper provides a new verification method which is useful for combinational circuits such as arithmetic circuits. The proposed method efficiently verifies whether a designed circuit satisfies a specification given by recurrence equations. This enables us to describe easily an error-free specification for arithmetic circuits. To perform verification efficiently using an ordinary OBDD package, an efficient truth-value rotation algorithm is developed. The truthvalue rotation algorithm efficiently generates an OBDD representing f(x + 1 (mod 2n)) from a given OBDD representing f(x). By experiments on SPARC station 10 model 51, it takes 180 secs to generate an OBDD for designed circuit of 23-bit square function, and additional 60 secs is sufficient to finish verifying that it satisfies the specification given by recurrence equations.

This paper introduces signal-controlled time-series modeling based on arbitrarily chosen buliding blocks. Such modeling is used in the design of a nested-form transver-sal structure based on Almost-Symmetrical ARMA (AS-ARMA) building blocks. This structure can operate in the transient mode, in contrast to the commonly used linear line-enhancers based on an conventional ARMA, leading to practically sound processing of short-duration signals. It is shown that the proposed time-series modeling can be effectively applied towards the separation of superimposed signals of heavily overlapping spectra.

Entire systems on a chip (SOCs) embodying a processor, memory, and system-specific peripheral hardware are now an everyday reality. The current generation of SOC designers are driven more than ever by the need to lower chip cost, while at the same time being faced with demands to get designs to market more quickly. It was to support this new community of designers that we developed Satsuki-an integrated processor synthesis and compiler generation system. By allowing the designer to tune the processor design to the bitwidth and performance required by the application, minimum cost designs are achieved. Using synthesis to implement the processor in the same technology as the rest of the chip, allows for global chip optimization from the perspective of the system as a whole and assures design portability. The integral compiler generator, driven by the same parameters used for processor synthesis, promotes high-level expression of application algorithms while at the same time isolating the application software from the processor implementation. Synthesis experiments incorporating a 0.8 micron CMOS gate array have produced designs ranging from a 45 MHz, 1,500 gate, 8-bit processor with a 4-word register file to a 31 MHz, 9,800 gate, 32-bit processor with a 16-word register file.

In conventional trellis coded modulation (TCM), higher-ary modulation scheme combining with a convolutional code is employed not to expand the transmitted bandwidth. This forces the system to be attended with signal constellation expansion and increasing the average signal power. As the solutions to avoid signal constellation expansion, TCM systems using totally overlapped signal sets (TO-TCM and RU-TCM) were proposed. These schemes can realize a coded modulation system without signal constellation expansion and achieve more coding gain compared with the conventional TCM. However, a problem that the systems with totally overlapped signal sets might be catastrophic has been remained. In this paper, we propose a novel TCM system using partially overlapped signal sets of non-equiprobable signaling (PO-TCM-NE). This scheme employs the partially overlapped signal constellation to control increasing signal points, and to avoid catastrophic error propagation. The non-equiprobable signaling is employed to reduce average signal power. Coding gain of the proposed PO-TCM-NE is considerably improved in consequence the average signal power is reduced much lower than that of other TCM systems with equiprobable signaling.

For the dependent protocols to perform the server-aided RSA secret computation, the damage caused by the active attacks is greater than that by the passive attacks. Though there are two dependent proposed protocols against active attacks, the cost of the two protocols is still high. In this paper, we propose two efficient dependent protocols. Even considering the low cost of these two protocols, they can also guard against the proposed active attacks.

M-ary orthogonal keying (MOK) systems under carrier frequency offset (CFO) are investigated. It is shown that spurious signals are introduced by the offset frequency components of spectrum after multiplication in correlation detection process, and some conditions on robust orthogonal signal sets are derived. Walsh function sets are found to be very weak against CFO, since they produce large spurious signals. As robust orthogonal signal sets against CFO, the rows of circulant Hadamard matrices are proposed and their error performanses are evaluated. The results show that they are good M-ary orthogonal signal sets in the presence of CFO.

This paper compares the performance of an indoor cellular system in terms of capacity and channel assignment delay for different Dynamic Channel Assignment (DCA) and Fixed Channel Assignment (FCA) schemes. We refer to specific group of DCAs, namely Channel Segregation and Reuse Partitioning (RP). Our main concern is to show that these DCA schemes offer better performance than FCA. Since the structure and floor layout of a building will have a major influence on the propagation and hence on the cell shape, a path loss simulator is developed for predicting the path loss which is used in evolving base station layouts. Computer simulation, based on Monte Carlo method, is carried out using the path loss values and the base station layouts. The results indicate that increased traffic capacity can be achieved with all DCAs in comparison with FCA. The highest capacity and a shorter channel assignment delay are delivered by Self-Organized Reuse Partitioning DCA scheme.

In this paper a new type of digital proxy signature is proposed. The proxy signature allows a designated person, called a proxy signer, to sign on behalf of an original signer. Classification of the proxy signatures is shown from the point of view of the degree of delegation, and the necessary conditions of a proxy signature are clarified. The proposed proxy signature scheme is based on either the discrete logarithm problem or the problem of taking the square root modulo of a composite number. Compared to the consecutive execution of the ordinary digital signature schemes, it has a direct from, and a verifier does not need a public key of a user other than the original signer in the verification stage. Moreover, it requires less computational work than the consecutive execution of the signature schemes. Due to this efficiency together with the delegation property, an organization, e.g. a software company, can very efficiently create many signatures of its own by delegating its signing power to multiple employees. Another attractive feature is that the proxy signature based on the discrete logarithm problem is highly applicable to other ordinary signature schemes based on the same problem, For instance, designated confirmer proxy signatures can be constructed. As a stronger form of proxy signature for partial delegation, another type of proxy signature scheme is proposed in which even an original signer cannot create a proxy signature. Furthermore, using a proposed on-line proxy updating protocol, the orignal signer can revoke proxies of dishonest proxy signers.

Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was developed. The technique can be applied to basic logic gates, full adders, multiplier units, and more complicated arithmetic logics like Conditional Carry Select (CCS) circuit. The magnitude of propagation delay time of RPL is smaller than the conventional CPL(Complementary Pass-transistor Logic), or DPL (Double Pass-transistor Logic). Low power consumption can also be achieved by reduced number of transistors and metal interconnections. Simulation and layout data also proved that RPL is advantageous over existing dual-rail logics while considering speed, power consumption and layout area.