Many efforts are currently underway to design wideband mobile communication systems. In this letter, we clarify the received signal level characteristics for wideband mobile radio channels in line-of-sight (LOS) microcells. We conduct several urban-area field experiments to measure the received signal levels for various receiver bandwidths from 300 kHz to 30 MHz and the power delay profile. The experimental results show that the fading depth of the received signal decreases as the normalized rms delay spread, defined as the product of receiver bandwidth and rms delay spread, increases. These results are useful in designing wideband microcell systems for urban areas.

Built-in self-test (BIST) has been applied to test an analog to digital converter (ADC) and a digital to analog converter (DAC) embedded in a DSP-core ASIC. The eight performance characteristics of the ADC and the DAC designed in accordance with the ITU-T recommendations are measured using the BIST. Three of the eight characteristics - the attenuation/frequency distortion, the variation of gain with input level, and the signal-to-total distortion - have been evaluated and the measured results have shown good agreement with measured results by conventional tests. In the BIST operation, the DSP-core generates input stimulus and analyzes output response by control of the self-test program, The sizes of the self-test program and coefficient data are 822 words of the IROM and 384 words of the data ROM, respectively. This area overhead is less than 0.5% of total chip area. Test-time by the BIST is reduced to approximately 3.2 seconds, which is one-tenth that of conventional testing. The mixed-signal DSP-core ASIC is testable with only logic test equipment, and as a result, test-cost - that is test investment and test-time - is reduced compared with conventional test methods.

This study proposes an amplitude limiting type spread spectrum communication to be applied to extremely low power radio wave communicaion and evaluates capability of the code division multiplex. First, changes in output from the correlation device, maximum power, and in allowable noise power are compared by computer simulation for the case where the number of multiplex channels is increased. Second, possible relationship between noise intensity and error rate is measured by actual loading experiments using a device developed for trial purpose. Third, majority decision logic is proposed for the said device to realize amplitude limiting type code division multiplex easily. When the amplitude is limited, the maximum power can be controlled at about 2 dB, and channels with more than half of the number of spread sign can be used. It is revealed that, in the spread spectrum, alteration of the number of multiplex channels is made easy by application of this method.

Digital-switching noise coupled into sensitive analog circuits is a critical problem in large-scale integration of mixed analog and digital circuits. This paper describes noise coupling of this kind, especially, through the substrate in CMOS integrated circuits, and reviews recent technical solutions to this noise problem. Simplified models have been developed to simulate the substrate coupling rapidly and accurately. A method using a CMOS comparator was proposed for measuring the effects of substrate noise, and equivalent waveforms of actual substrate noise were obtained. A circuit tecnique, called active guard band filtering, that controls the noise source is a new approach to substrate noise decoupling. CAD methods for handling substrate-coupled switching noise are making design verification possible for practical mixed-signal LSIs.

A new structure for adaptive AR spectral estimation based on multi-band decomposition of the linear prediction error is introduced and the mathematical background for the soulution of the related adaptive filtering problem is derived. The presented structure gives rise to AR spectral estimates that represent the true underlying spectrum with better fidelity than conventional LS methods by allowing an arbitrary trade-off between variance of spectral estimates and tracking ability of the estimator along the frequency spectrum. The linear prediction error is decomposed through a filter bank and components of each band are analyzed by different window lengths, allowing long windows to track slowly varying signals and short windows to observe fastly varying components. The correlation matrix of the input signal is shown to satisfy both time-update and order-update properties for rectangular windowing functions, and an RLS algorithm based on each property is presented. Adaptive forward and backward relations are used to derive a mathematical framework that serves as a basis for the design of fast RLS alogorithms. Also, computer experiments comparing the performance of conventional and the proposed multi-band methods are depicted and discussed.

This letter presents a realization of active current-mode resonator with complex coefficients using CCIIs. The resonator can be used for cascade or leapfrog configuration of high-order bandpass filters with complex coefficients. For realizing the resonators, only the grounded capacitors and the grounded resistors as passive elements are required, therfore the resonator is suitable for the integrated circuit realization. The letter shows that the response error of the proposed circuit caused by nonideality of active components is more easily compensated than that of voltage-mode counterpart. Experimental result is used for verifying the feasibility of the proposed resonator.

A formal system-level synthesis model for the concurrent object-oriented design of parallel computer systems, called Multi-token Object-oriented Bi-directional net (MOBnet), is proposed. The MOBnet model extends the standard Petri net by defining (1) multiple tokens to represent different kinds of synthesis control information, (2) object-oriented nodes (places) to denote the system parts under synthesis, and (3) bi-directional arcs to model the design completion check and synthesis rollback operations. In this paper, we first show that MOBnet can serve as a pre-fabrication design methodology analysis tool in ways such as class hierarchy construction, design specification comparison, reachability analysis, and concurrent process management and analysis. We then formally prove MOBnet to be a valid model for concurrent synthesis and give experimental application examples to verify. Finally, solution schemes for the design completion check and synthesis rollback problems are formally validated by analyzing the dynamic behavior of MOBnet, and experimentally illustrated through examples.

This paper discusses the problems in designing virtual-path (VP) networks and underlying transmission-path (TP) networks using the "self-sizing" capability. Self-sizing implies an autonomous adjustment mechanism for VP bandwidths based on traffic conditions observed in real time. The notion of "bandwidth demand" has been introduced to overcome some of the problems with VP bandwidth sizing, e.g., complex traffic statistics and diverse quality of service requirements. Using the bandwidth demand concept, a VP-bandwidth-sizing procedure is proposed in which real-time estimates of VP bandwidth demand and successive VP bandwidth allocation are jointly utilized. Next, TP bandwidth demand, including extra capacity to cover single-link failures, is defined and used to measure the congestion level of the TP. Finally, a TP provisioning method is proposed that uses TP "lifetime" analysis.

In this paper, we present a first step for developing a method of verifying both safety and correctness of object-oriented design specification. At first, we analyze the discrepancies, which can occur between requirements specification and design specification, to make clear target faults. Then, we propose a new design review method which aims at detecting faults in the design specification by using three kinds of information tables. Here, we assume that component library, standards for safety and design specification obtained from the Booch's object-oriented design method are given. At the beginning, the designers construct a design table based on a design specification, and the verifiers construct a correctness table and a safety table from component library and standards for safety. Then, by comparing the items on three tables, the verifiers review a given design specification and detect faults in it. Finally, using a small example of object-oriented design specification, we show that faults concerning safety or correctness can be detected by the new design review method.

Two high output-resistance CMOS current mirrors suitable for a low-voltage operation and achieving a high output-swing are presented. They incorporate a modified regulated-cascode, which employs a current-mode amplifier. The main architecture concepts and their detailed schematic examples are discussed. SPICE simulation comparison is shown and the properties of each architecture are pointed out.

The present paper examines a two-dimensional (2-D) joint-process lattice estimator and its implementation for image restoration. The gradient adaptive lattice (GAL) algorithm is used to update the filter coefficients. The proposed adaptive lattice estimator can represent a wider class of 2-D FIR systems than the conventional 2-D lattice models. Furthermore, its structure possesses orthogonality between the backward prediction errors. These results in superior convergence and tracking properties versus the transversal and other 2-D adaptive lattice estimators. The validity of the proposed model for image restoration is evaluated through computer simulations. In the examples, the implementation of the proposed lattice estimator as 2-D adaptive noise cancellator (ANC) and 2-D adaptive line enhancer (ALE) is considered.

We review a fundamental weak point of the OSS digital signature scheme against cryptanalysis by Pollard et al., and propose a new scheme of digital signature which overcomes this defect. More specifically, instead of the ring of the rational integer, we use the ring of integral quaternions, which is a non-commutative Euclidean ring. Known attacks to OSS signature do not work our scheme due to the non-commutativity. On the other hand, this scheme causes little increase in the burden of generation and verification of digital signature for the legitimate users, with respect to the original OSS scheme.

This paper proposes a time-dependent gateway earth station (GES) assignment method for a user terminal in non-geostationary orbiting satellite systems. Time-dependent nature of the GES service area is first discussed for an example intermediate circular orbit system. Then, the time-dependent GES assignment method is proposed. Finally, the advantage of the proposed method is shown by several calculation results.

In this paper, we propose a practical and secure electronic voting scheme which meets the requirements of large scale general elections. This scheme involves voters, the administrator or so called the government and some scrutineers. In our scheme, a voter only has to communicate with the administrator three times and it ensures independence among voters without the need of any global computation. This scheme uses the threshold cryptosystem to guarantee the fairness among the candidate's campaign and to provide mechanism for achieving the function that any voter can make an open objection to the tally if his vote has not been published. This scheme preserves the privacy of a voter against the administrator, scrutineers, and other voters. Completeness, robustness, and verifiability of the voting process are ensured and hence no one can produce a false tally, corrupt or disrupt the election.

Transport-processing FPGAs have been proposed for flexible telecommunication systems. Since those FPGAs have finer granularity of logic functions to implement circuits on them, the amount of routing resources tends to increase. In order to keep routing congstion small, it is necessary to execute placement and routing simultaneously. This paper proposes a simultaneous placement and global routing algorithm for transport-processing FPGAs whose primary objective is minimizing routing congestion. The algorithm is based on hierarchical bipartition of layout regions and sets of LUTs (Look Up Tables) to be placed. It achieves bipartitioning which leads to small routing congestion by applying a network flow technique to it and computing a maximum flow and a minimum cut. If there exist connections between bipartitioned LUT sets, pairs of pseudo-terminals are introduced to preserve the connections. A sequence of pseudo-terminals represents a global route of each net. As a result, both placement of LUTs and global routing are determined when hierarchical bipartitioning procedures are finished. The proposed algorithm has been implemented and applied to practical transport-processing circuits. The experimental results demonstrate that it decreases routing congestion by an average of 37% compared with a conventional algorithm and achieves 100% routing for the circuits for which the conventional algorithm causes unrouted nets.

The inclusion of the non-quasi-static effect is crucial in the simulation of the microwave circuits for MOS transistors. This report proposes a simple model which includes this effect in small-signal simulation. The simulated results are consistent with the measured data up to a frequency that is 30 times higher frequency than the cut-off frequency.

This paper presents a method for simply estimating characteristics of signals received by a millimeter wave car radar. In this method, the substitution of a radar target with a set of scattering points is introduced to take account of the phenomenon that only a part of the target is irradiated with the radio wave from the radar antenna with a sharp beam; the phenomenon is peculiar to the car radar which operates in a compact range. The positions of these scattering points and the RCS values for the scattering points are appropriately determined on the basis of a measured RCS image for the target. The RCS image means a spatial distribution of RCS values on the surface of the target. In addition, influence of the ground, which is a dominant clutter in car radar environments, and characteristics of the car radar hardware can be included in the estimation method. The estimated characteristics of the signal received by the car radar are compared with the measured ones under typical cases in the car radar environments. The comparison verifies not only that the received signal characteristics are well estimated even when the range is rather short but also that the substitution of the target with scattering points is valid. The proposed method can realize the estimation of the received signal characteristics. Furthermore, the method can be developed into a computer simulation for evaluating the target detection performance of the car radar.

A matched filter (Mf) based on analog filter technology for DS-CDMA mobile radio is presented. An experimental one-chip LSI of AMF is developed for measuring various areas of performance such as power consumption, cut-off frequency, and linearity. The measurements show that power consumption is only 110mW at a voltage supply of 3V and an operational clock frequency of 25 MHz. We implemented a RAKE combiner using experimental AMF LSI and measured the bit error rate (BER) performance of DS-CDMA signal transmission in a multipath fading environment.

This paper reports on a high-speed silicon bipolar transistor with an fT and fMAX of over 40 GHz, we call it the Advanced Boro-silicated-glass Self-Aligned (A-BSA) transistor. In basic BSA technology, a CVD-BSG film is used not only as a diffusion source to form the intrinsic base and the link base regions but also as a sidewall spacer between the emitter and the base polysilicon electrodes. An A-BSA transistor offers three advancements to this technology: (1) a graded collector profile underneath the intrinsic base region to suppress the Kirk effect; (2) an optimized design of the link base region to prevent the frade-off effect between fT and base resistance; and (3) a newly developed buried emitter electrode structure, consisting of an N++-polysilicon layer, a platinum silicide layer, and a CVD tungsten plug, to prevent the emitter plug effect. Furthermore, our transistor uses a BPSG filled trench isolation to reduce parasitic capacitance and improve circuit performance. In this paper, we describe device design, process technology and characterization of the A-BSA transistor, with it we have performed several application ICs, operating at 10Gb/s and above. The A-BSA transistor achieved an fT of 41 GHz and an fMAX of 44 GHz under optimized conditions.

A low power consumption 16-bit fixed point Digital Signal Processor (DSP) has been developed to realize a half-rate CODEC for the Personal Digital Cellular (PDC) system. Dual datapath architecture has been employed to execute multiply-accumulate (MAC) operations with a high degree of efficiency. With this architecture. 86.3% of total MAC operations in the Pitch Synchronous Innovation Code Excited Linear Prediction (PSI-CELP) program are executed in parallel, so that total instruction cycles are reduced by 23.1%. The area overhead for the dual datapath architecture is only 3.0% of the total area. Furthermore, in order to reduce power consumption, circuit design techniques are also extensively applied to RAMs. ROMs, and clock circuits, which consume the great majority of power. By reducing the number of precharging bit lines, a power reduction of 49.8% is achieved in RAMs, and above 40% in ROMs. By applying gated clock to clock lines, a power reduction of 5.0% is achieved in the DSP that performs the PSI-CELP algorithm. The DSP is fabricated in 0.5 µm single-poly, double-metal CMOS technology. The PSI-CELP algorithm for the PDC half-rate CODEC can operate at 22.5 MHz instruction frequency and 1.6 V supply voltage. resulting in a low-power consumption of 28 mW.