Many digital signal processors (DSPs) employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often leads to overhead. This paper presents methods to efficiently allocate addresses for variables in a given program so that overhead in AR update operations is reduced. Memory addressing model is generalized in such a way that AR can be updated at the codes without memory accesses. An efficient memory address allocation is obtained by a method based on the graph linearization algorithm, which takes account of the number of possible AR update operations for every memory access. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for µPD77230 (NEC) and generated codes for several examples prove effectiveness of these methods.

A 100MIPS high speed and low power fixed point Digital Signal Processor (DSP) has been developed applying 0.45µm CMOS TLM technology. The DSP contains a 16-bit32K full CMOS static RAM with a hierarchical low power architecture. The device is a RAM based DSP with a total of 4.2 million transistors and a new low power design and process which enabled an approximate 50% reduction in power as compared to conventional DSPs at 40 MHz. In order to cover very wide application requirements, this DSP is capable of operating at 1.0 V for DSP core and 3.3 V for I/O. This was achieved by new level shifter circuitry to interface with cost effective 3 V external commodity products and confirmed 80% of power reduction at Core VDD=2.0 V, I/O VDD=3.3 V at 40MHz. This paper describes the new features of the high speed and low power DSP.

This letter proposes and investigates a method of estimating the direction of arrival (DOA) of wideband signals such as spread spectrum signals, in a multipath channel. The DOA estimation method can reduce the effect of signal distortion due to bandwidth of signals by creating a spatial spectrum wihch satisfies the sampling theory in the time domain. The DOA estimate calculated from this spatial spectrum is robust against signal distortion due to multipath. Computer simulations numerically evaluate the proposed method. In comparison with conventional MUSIC algorithm, the proposed method achieves superior performance in a multipath channel.

This paper propeses advanced multi-stage interference canceller systems (MSICS) wihch can estimate radio channels with precision in the direct sequence code division multiple access (DS-CDMA) systems. For the accurate channel estimations, we propose a novel radio channel estimation method specified by the following two signal processing methods. One is the radio channel estimation using both pilot and information signals. The other is the correction of estimated radio channels using adaptation algorithm based on the least mean square method (LMS). The results of our computer simulation indicate that the cell capacity of the advanced MSICS in serial and parallel structure can be increased by about 1.8 and 1.3 times over that of a receiver which does not has a canceller, respectively. Moreover, the advanced MSICS in serial and parallel structure can reduce the required Eb/No by about 1.2 dB and 1.6 dB at a BER of 10-3 compared to the Eb/No of a basic MSICS, respectively.

This paper presents a method to examine the effect of introducing data application services on existing wireless CDMA networks where conventional voice communications service is being provided. Since the total number of channels used in a cell is limited in the interfering cellular environments, some voice-traffic channels should be sacrificed when an additional channel is introduced for data services. We investigate this trade-off by analyzing the interference the forward link channels generate. It is also an objective of this paper to examine the forward link capacity in terms of the numbers of paging and voice-/data-traffic channels so as to determine the impact of introducing data services via paging and traffic channels. Different capacity regions are plotted for various cellular environments.

In this paper, we propose a two-dimensional (2-D) least-squares lattice (LSL) algorithm for the general case of the autoregressive (AR) model with an asymmetric half-plane (AHP) coefficient support. The resulting LSL algorithm gives both order and space recursions for the 2-D deterministic normal equations. The size and shape of the coefficient support region of the proposed lattice filter can be chosen arbitrarily. Furthermore, the ordering of the support signal can be assigned arbitrarily. Finally, computer simulation for modeling a texture image is demonstrated to confirm the proposed model gives rapid convergence.

In the last few years analog adaptive filters have been a subject of active research because they have the ability to handle in real time much higher frequencies, with a smaller size and lower power consumption that their digital counterparts. During this time several analog adaptive filter algorithms have been reported in the literature, almost all of them use the continuous time version of the least mean square (LMS) algorithm. However the continuous time LMS algorithm presents the same limitations than its digital counterpart, when operates in noisy environments, although their convergence rate may be faster than the digital versions. This fact suggests the necessity of develop analog versions of recursive least square (RLS) algorithm, which in known to have a very low sensitivity to additive noise. However a direct implementation of the RLS in analog way would require a considerable effort. To overcome this problem, we propose an analog RLS algorithm in which the adaptive filter coefficients vector is estimated by using a fully connected network that resembles a Hopfield network. Theoretical and simulations results are given which show that the proposed and conventional RLS algorithms have quite similar convergence properties when they operate with the same sampling rate and signal-to-noise ratio.

Nyberg and Rueppel recently proposed a new EIGamal-type digital signature scheme with message recovery feature and its six variants. The advantage of small signed message length is effective especially in some applications like public key certifying protocols or the key exchange. But two forgeries that present a real threat over such applications are pointed out. In certifying public keys or key exchanges, redundancy is not preferable in order to store or transfer small data. Therefore the current systems should be modified in order to integrate the Nyberg-Ruepple's signature into such applications. However, there has not been such a research that prevents the forgeries directly by improving the signature scheme. In this paper, we investigate a condition to avoid the forgeries directly. We also show some new message recovery signatures strong against the forgeries by adding a negligible computation amount to their signatures, while not increasing the signature size. The new scheme can be integrated into the above application without modifying the current systems, while maintaining the security.

The capture effect caused by some of power assignment, Rayleigh fading, and near-far effect, can improve the performance of random-access techniques in mobile radio environment. Moreover, if we consider the overall effect of them, the system performance can be noticeably improved. In this paper, the combined effect of fixed power assignment scheme, Rayleigh fading, and near-far effect on the performance of slotted ALOHA are studied. Plus, the performance degradation caused by AWGN is also investigated. The type of signal capture to be considered is the one that a signal involved in a collision survives if its power level exceeds the sum of the other signals participating in the same collision. Numerical calculations are used to demonstrate the degree of improvement and degradation.

A method for recovering the LPC spectrum from a microphone array input signal corrupted by less directional ambient noise is proposed. This method is based on the subspace method, in which directional signal and non-directional noise is classified in the subspace domain using eigenvalue analysis of the spatial correlation matrix. In this paper, the coherent subspace (CSS) method, a broadband extension of the subspace method, is employed. The advantage of this method is that is requires a much smaller number of averages in the time domain for estimating subspace, suitable feature for frame processing such as speech recognition. To enhance the performance of noise reduction, elimination of noise-dominant subspace using projection is further proposed, which is effective when the SNR is low and classification of noise and signals using eigenvalue analysis is difficult.

We consider the problem of estimating one- and two-dimensional direction of arrivals for arbitrary plane waves in an incoherent/coherent source environment. For the one-dimensional case, we use matrix pencil (MP) method developed by Y. Hua for signal-poles estimation. We then extend this method to estimate the two-dimensional direction of arrivals (2D-DOA), resulting in the "Extended Matrix Pencil" (EMP) method. This method can be applied successfully as much for an incoherent source environment as for a coherent source environment. To study the performance of these methods, in both cases results are compared with the "Total Least Squares-Estimation of Signal Parameters via Rotational Invariance Techniques" (TLS-ESPRIT) and the "Spatial Smoothing-TLS-ESPRIT" (SS-TLS-ESPRIT) methods. The results show that the MP method estimates the DOA more accurately and better than the TLS-ESPRIT and the SS-TLS-ESPRIT, even with few snapshots. Simulation results show that the EMP method, presented in this paper, estimates the 2-DOA better than the other two methods used for comparison.

Clothoid or cornu spiral segments were used as transition spirals forming C-and S-shaped curves between circles as well as straight lines in various situations of highway road design. These transitions are the center lines of rail, highway road design. The above C and S-shaped form curves consist one or more transition segments. We study the possibility of using the single transition spirals in the situations that use many transition spirals to form smooth transition spline between circles as well as straight lines. We also compute the bounds for the scaling of such single spirals using the practical equation. This paper is aimed to give a method avoiding non-linear equations by finding range for the scaling factor of the clothoids which can take initially an appropriate closer value from this range.

The EMC-adequate design of microelectronic systems includes all actions intended to eliminate electromagnetic interference in electronic systems. Challenges faced in the microelectronic area include a growing system complexity, high integration levels and higher operating speeds at all levels of integration (chip, MCM, printed circuit board and system). The growing complexity, denser design and higher speed all lead to a substantial increase in EMC problems and accordingly the design time. EMC is not commonly accepted as a vital topic in microelectronic design. Microelectronic designers often are of the opinion that EMC is limited to electrical and electronic systems and the mandatory product regulations instead of setting requirements also for the integrated circuit they are designing. In this contribution a concept for an EMC-adequate design of electronic systems will be introduced. This concept is based on a generalized development process to integrate EMC-constraints into the system design. A prototype of an environment to analyse signal integrity effects on PCB based on a workflow oriented integration approach will be presented. Based on this approach the generation of user specific design and analysis environments including various set of EMC-tools is possible.

In this paper we propose a comprehensive approach to physical design based on the constraint paradigm. Bounds on the most critical circuit parasitics are automatically generated to help designers and/or physical design tools meet a set of high-level specifications. The constraint generation engine is based on constrained optimization, where various parasitic effects on interconnect and devices are accounted for and dealt with in different manners according to their statistical behavior and their effect on performance.

This paper proposes the signaling network deployment for mobile networks with a goal of reducing the signaling cost and time to set up calls. In this deployment, we solve the heavy concentration of signaling traffic resulting from the centralized database used in current mobile networks. The solution exploits the features of the distributed databases, data partition, locality of mobile users, and Common Channel Signaling System No.7 (CCSS No.7) network architectures. We assume the area served by the mobile network is partitioned into a few zones. There is a database associated with each zone. A numbering database strategy is proposed in this paper for the mobiles to register at some specific nearby databases according to their mobile identification numbers. Thus, a calling party can directly locate the called party by the mobile identification number he/she dialed. This method can reduce over 95% of the location-updating cost and 70% of the location-tracking cost under a general sumulation model. We also present the implementation considerations of this strategy. This implementation is an enhancement of the routing function of the Signaling Connection Control Part in CCSS No.7 protocol stacks. With few modifications on current mobile networks, the proposed strategy can obtain very excellent results.

In layout design of transport-processing FPGAs, it is required that not only routing congestion is kept small but also circuits implemented on them operate with higher operation frequency. This paper extends the proposed simultaneous placement and global routing algorithm for transport-processing FPGAs whose objective is to minimize routing congestion and proposes a new algorithm in which the length of each critical signal path (path length) is limited within a specified upper bound imposed on it (path length constraint). The algorithm is based on hierarchical bipartitioning of layout regions and LUT (Look Up Table) sets to be placed. In each bipartitioning, the algorithm first searches the paths with tighter path length constraints by estimating their path lengths. Second the algorithm proceeds the bipartitioning so that the path lengths of critical paths can be reduced. The algorithm is applied to transport-processing circuits and compared with conventional approaches. The results demonstrate that the algorithm satisfies the path length constraints for 11 out of 13 circuits, though it increases routing congestion by an average of 20%. After detailed routing, it achieves 100% routing for all the circuits and decreases a circuit delay by an average of 23%.

We propose a top-down approach for cosimulation of hardware/software co-designs for embedded systems and introduce a component logical bus architecture as an interface between software components implemented by processors and hardware components implemented by custom logic circuits. Co-simulation using a component logical bus architecture is possible is the same environment from the stage at which the processor is not yet finalized to the stage at which the processor is modeled in register transfer language. Models based upon a component logical bus architecture can be circulated and reused. We further describe experimental results of our approach.

Recently, two new efficient server-aided RSA secret computation protocols were proposed. They are efficient and can guard against some active attacks. In this letter, we propose two multi-round active attacks which can effectively reduce their security level even break them.

A novel cryptographic key assignment scheme for dynamic access control in a user hierarchy is presented. Based on Rabin's public key system and Chinese remainder theorem, each security class SCi is assigned a secret key Ki and some public parameters. In our scheme, a secret key is generated in a bottom-up manner so as to reduce the computation time for key generation and the storage size for public parameters. We also show that our proposed scheme is not only secure but also efficient.

A modified cryptographic key assignment scheme for the dynamic access control in a group-oriented user hierarchy is presented. In the partially ordered set (poset, for short) user hierarchy (GjGi) embedded in a group-oriented (t, n) threshold cryptosystem, the source group Gi has higher security clearance to access the information items held in the target group Gj. If a target group Gj has multipe paths reachable from a source group Gi, we must choose the least cost path to rapidly resolve the dynamic access control problem Furthermore, multiple threshold values are also considered in order to meet the different security requirements.