This paper presents a new routing method that takes into account neighboring-wire-capacitance (inter-layer and intra-layer) constraints. Intermediate routing (IR) assigns each H/V wire segment to the detailed routing (DR) grid using global routing (GR) results, considering the neighboring-wire constraints (NWC) for critical nets. In DR, the results of IR for constrained nets and their neighboring wires are preserved, and violations that occur in IR are corrected. A simple method for setting NWC that satisfy the initial wire capacitance given in a set-wire-load (SWL) file is also presented. The routing method enables more accurate delay evaluation by considering inter-wire capacitance before DR, and avoids long and costly turnaround in deepsubmicron layout design. Experimental results using MCNC benchmark test data shows that the errors between the maximum delay from IR and that from DR for each net were less than 5% for long (long delay) nets.

Providing various assistances for design modifications on HDL source codes is important for design reuse and quick design cycle in VLSI CAD. Program slicing is a software-engineering technique for analyzing, abstracting, and transforming programs. We show algorithms for extracting/removing behaviors of specified signals in VHDL descriptions. We also describe a VHDL slicing system and show experimental results of efficiently extracting components from VHDL descriptions.

For the improvement of software quality and productivity, the author aims at realizing a software development environment to develop software through utilizing the merits of group work. Since networking is necessary for collaborative software development, he has developed a software distributed development environment for collaborative software development. In this environment, discussions about software design are held through a communication network, and the contents of discussions are recorded as software design decisions and decision rationale. One feature of this environment is that the contents of discussions can be recorded in on-line real time and reused without reconstructing the information recorded through this environment. This paper clarifies the essential conditions for actualizing this environment and proposes an information structure model for recording the contents of discussions that actualizes the above-mentioned feature. The effectiveness of the proposed model is proved through an example of its application to software design discussions.

In this paper, we propose a new register transfer level (RT level) testability analysis method. Controllability and observability measures are defined for signal vectors based on the numbers of values they can take. The control part and the datapath part are automatically identified in the given RT level model and distinctive analysis methods are applied. We also describe a DFT point selection method based on our testability measures. In a experiment on a signal processing circuit whose gate count is 7690 including 578 FFs, almost the same fault coverage is achieved with fewer scan FFs than a conventional method based on gate level testability analysis.

This paper presents a timing-driven global routing algorithm based on coarse pin assignment, block reshaping, and positioning for VLSI building block layout. As opposed to conventional approaches, we combine pin assignment and global routing problems into one problem. The proposed algorithm determines global routes, coarse pin assignments, and block shapes and positions so as to minimize the chip area and total wire length of nets under the given timing constraints. It is based on an iterative improvement paradigm and performs rip-up and rerouting, block reshaping, and positioning in the manner of simulated evolution taking shapes of soft blocks and routing congestion into consideration until the solution is not further improved. The Elmore delay model is adopted for the interconnection delay model. Experimental results show the effectiveness of the proposed algorithm.

In the ITS (Intelligent Transport Systems), it is an essential condition (mixed environment) that vehicles that have communication equipment and vehicles that do not have it simultaneously run in the same road. In this paper, a vehicular driving assistant system that is applicable to the mixed environment is proposed. The proposed system uses spread spectrum techniques and consists of several new systems such as a PN code assignment system, new vehicle position systems, and a vehicle map update system. In the proposed system, the wireless broadcast CDMA is used for inter-vehicle communications. This paper also shows preexaminations of the proposed system by using an autonomous traffic flow simulator including inter-vehicle communications. It is shown that the traffic safety can be improved by using inter-vehicle communications.

This paper describes code assignment and the multicode sense scheme for an inter-vehicle CDMA communication network. When considering an inter-vehicle broadcasting CDMA communication network, spreading code assignment and notification problems arise. In such a CDMA network, the use of common codes is a solution. Then an objective function of common code assignment in an IVCN is formulated as a combinatorial optimization problem. In addition, a multicode sense (MCS)/CDMA system is proposed as a simple code assignment scheme. Computer simulations show that the MCS/CDMA system can autonomously perform spatial rearrangement of the common codes using only local information that each vehicle can obtain by sensing the code channels.

A key distribution system is a system in which users securely generate a common key. One kind of identity-based key distribution system was proposed by E. Okamoto. Its security depends on the difficulty of factoring a composite number of two large primes like RSA public-key cryptosystem. Another kind of identity-based key distribution system was proposed by K. Nyberg, R. A. Rueppel. Its security depends on the difficulty of the discrete logarithm problem. On the other hand, Koblitz and Miller described how a group of points on an elliptic curve over a finite field can be used to construct a public key cryptosystem. In 1997, we proposed an ID-based key distribution system over an elliptic curve, as well as those over the ring Z/nZ. Its security depends on the difficulty of factoring a composite number of two large primes. We showed that this system over an elliptic curve is more suitable for the implementation than those over the ring Z/nZ. In this paper, we apply the Nyberg-Rueppel ID-based key distribution system to an elliptic curve. It provides relatively small block size and high security. This public key distribution system can be efficiently implemented. However the Nyberg-Rueppel's scheme requires relatively large data transmission. As a solution to this problem, we improve the scheme. This improved scheme is very efficient since data transferred for the common key generation is reduced to half of those in the Nyberg-Rueppel's scheme.

The development of saturation diving in civil and defense applications has enabled man to work in the sea at great depths and for long periods of time. This advance has resulted, in part, as a consequence of the substitution of helium for nitrogen in breathing gas mixtures. However, utilization of HeO2 breathing mixture at high ambient pressures has caused problems in speech communication; in turn, helium speech enhancement systems have been developed to improve diver communication. These speech unscramblers attempt to process variously the grossly unintelligible speech resulting from the effect of breathing mixtures and ambient pressure, and to reconstruct such signals in order to provide adequate voice communication. It is known that the glottal excitation is quasi-periodic and the vocal tract filter is quasi-stationary. Hence, it is possible to use an auto regressive modelisation to restore speech intelligibility in hyperbaric conditions. Corrections are made on the vocal tract transfer function, either in the frequency domain, or directly on the autocorrelation function. A spectral subtraction or noise reduction may be added to improve speech quality. A new VAD enhanced helium speech unscrambler is proposed for use in adverse conditions or in speech recognition. This system, implementable on single chip DSP of current technology, is capable to work in real time.

Privacy, voter uncoercibility, collision freedom, verifiability, and tally correctness are essential properties of modern electronic election systems. None of the single-authority election systems proposed in the literatures achieves all the above five properties. In this paper we propose a universal single-authority election system that satisfies the five properties. In particular, the privacy of each voter is protected against the authority and other voters, and no voter can coerce any other voter into changing the value of his vote in our proposed system. We also show that it is impossible for a collision-free single-authority election system to possess the voter uncoercibility and authority uncoercibility at the same time.

The DC component suppressing method, called Guided Scrambling (GS), has been proposed, where a source bit stream within a data block is subjected to several kinds of scrambling and a RLL (Run Length Limited) coding to make the selection set of channel bit streams, then the one having the least DC component is selected. Typically, this technique uses a convolutional operation or GF (Galois field) conversion. A review of their respective symbol error properties has revealed important findings. In the former case, the RS (Reed-Solomon) decoding capability is reduced because error propagation occurs in descrambling. In the latter case, error propagation of a data block length occurs when erroneous conversion data occurs after RS decoding. This paper introduces expressions for determining the decoded symbol error probabilities of the two schemes based on these properties. The paper also discusses the difference in code rates between the two schemes on the basis of the result of calculation using such expressions.

A multicarrier modulation called orthogonal frequency division multiplex (OFDM) is attracting attention as a transmission scheme which is robust against multipath propagation. A major disadvantage of OFDM is that it is sensitive to nonlinear distortion due to its wide transmission amplitude range. The scope of this study is to cope with the nonlinear problem. We propose a nonlinear distortion compensation scheme using an iterative method which has been applied to an image signal restoration.

This paper describes a new architecture-based DSP processor, which consists of n n mesh multiprocessor for digital signal processing. A prototype chip, RCDSP9701 has been designed and implemented using a CMOS 0. 6 µm process. This architecture has better performance compare to the traditional microprocessor solution to Digital Signal Processing. The proposed method poses remarkable flexibility compare to ASIC (Application Specified Integrated Circuits) approach for Digital Signal Processing applications. In addition, the proposed architecture is fault tolerant and suitable for parallel computing applications. In this paper, an implementation into a silicon chip of the new architecture is presented to give a better understanding of our work.

This paper proposes a new method for dynamically controlling the clock speed of a processor in order to reduce power consumption without decreasing system performance. It automatically tunes the processor's speed by monitoring its activities and avoiding useless work so as not to exhaust the battery energy. Experiments with performance bottlenecks caused by disk activities show that the proposed method is very effective in comparison with the traditional one, in which the processor's speed is fixed.

The required building blocks of CMOS fuzzy chips capable of performing as adaptive fuzzy systems are described in this paper. The building blocks are designed with mixed-signal current-mode cells that contain low-resolution A/D and D/A converters based on current mirrors. These cells provide the chip with an analog-digital programming interface. They also perform as computing elements of the fuzzy inference engine that calculate the output signal in either analog or digital formats, thus easing communication of the chip with digital processing environments and analog actuators. Experimental results of a 9-rule prototype integrated in a 2. 4-µm CMOS process are included. It has a digital interface to program the antecedents and consequents and a mixed-signal output interface. The proposed design approach enables the CMOS realization of low-cost and high-inference fuzzy systems able to cope with complex processes through adaptation. This is illustrated with simulated results of an application to the on-line identification of a nonlinear dynamical plant.

The most basic cross-talk minimization problem is to assign given n intervals to n parallel tracks where the cross-talk is defined between two intervals assigned to the adjacent tracks with the amount linear to parallel running length. This paper solves the problem for the case when any pair of intervals intersects and the objective is to minimize the sum of cross-talks. We begin the discussion with the fact that twice the sum of lengths of n/2 shortest intervals is a lower bound. Then an interval set that attains this lower bound is characterized with a simple assignment algorithm. Some additional considerations provide the minimum cross-talk for the other interval sets. The main procedure is to sort the intervals twice with respect to the length of left and right halves of intervals.

This letter presents a new algorithm for improving the Signal to Noise Ratio (SNR) of complex sinusoidal signals contaminated by additive Gaussian noises using sum of Higher-Order Statistics (HOS). We conduct some computer simulations to show that the proposed algorithm can improve the SNR more than 7 dB compared with the conventional coherent integration when the SNR of the input signal is -10 dB.

This paper presents Power-Pro architecture (Programmable Power Management Architecture), a novel processor architecture for power reduction. The Power-Pro architecture has two key functionalities: (i) Supply voltage and clock frequency of a microprocessor can be dynamically varied, and (ii) active datapath width can be dynamically adjusted to the precision of each operation. The most unique point of this architecture is that software programmers can directly specify the requirements of applications such as real-time constraints and precision of the operations. To make programmable power management possible, Power-Pro architecture equips special instructions. Programmers can vary the supply voltage, the clock frequency and the active datapath width dynamically by the instructions. Experimental results show that power consumption for a variety of applications are dramatically reduced by the Power-Pro architecture.

In this paper, we present a hierarchical technique for simultaneous pin assignment and global routing during floorplanning based on the minimum cost maximum integer flow algorithm with several heuristic cost functions. Furthermore, our algorithm handles feedthrough pins and equi-potential pins taking into account global routes. Our algorithm allows various user specified constraints such as pre-specified pin positions, wiring paths, wiring widths and critical nets. Experimental results including Xerox floorplanning benchmark have shown the effectiveness of the heuristics.

The checkerboard effect is caused by the periodic time-variant property of multirate filters which consist of up-samplers and digital filters. Although the conditions for some one-dimensional (1D) multirate systems to avoid the checkerboard effect have been shown, the conditions for Multidimensional (MD) multirate systems have not been considered. In this paper, some theorems about the conditions for MD multirate filters without checkerboard effect are derived. In addition, we also consider MD multirate filter banks without checkerboard effect. Simulation examples show that the checkerboard effect can be avoided by using the proposed conditions.