A new high performance digital signal processor (DSP) that lowers power consumption, reduces chip count, and enables system cost savings for wireless communications applications was developed. The new device contains high performance, hard-wired functionality with a specialized instruction set to effectively implement the worldwide digital cellular standard algorithms, including GSM, PDC and NADC, and also features both full rate and future half rate processing by software modules. The device provides a wider operating voltage ranging from 1.5 V to 5.5 V using 5 V process based on the market requirement of 5 V supply voltage, even though a power supply voltage in most applications will be shifted to 3 V. Several circuits was newly developed to achieve low power consumption and high speed operation at both 5 V and 3 V process using the same data base. The device also features over 50 MIPS of processing power with low power consumption and 100 nA stand-by current at either 3 V or 5 V. One remarkable advantage is a flexible CPU core approach for the future spin-off devices with different ROM/RAM configurations and peripheral modules without requiring any CPU design changes. This paper describes the architecture of a lower power and high speed design with effective hardware and software modules implementations.

We propose a distributed operation system platform for optical cable networks. This distributed platform is an extension of the previously proposed platform for a flexible cable network operation. The concept of the unit platform has been proposed for the distributed operation system platform. By using this concept, we discuss the system upgrade including the connection to other operation systems. We use an object-oriented software technology for designing the distributed operation system platform. The prototype system has been constructed using C++ programing language and the evaluated results are shown.

In this paper we describe a method for resynthesizing the controller of a design for a fixed datapath with the objective of increasing the design's throughput by minimizing its total execution time. This work has tremendous potential in two important areas: one, design reuse for retargetting datapaths to new libraries, new technologies and different bit-widths; and two, back-annotation of physical design information during High-Level Synthesis (HLS), and subsequent adjustment of the design's schedule to account for realistic physical design information with minimal changes to the datapath. We present our approach using various formulations, prove optimality of our algorithm and demonstrate the effectiveness of our technique on several HLS benchmarks. We have observed improvements of up to 34% in execution time after straightforward application of our controller resynthesis technique to the outputs of HLS.

We have developed a method to automatically generate a multi-input-adder circuit for an irregular array of partial products. "FASTOOL," an FIR Filter Automatic Synthesis TOOL for an HDL design environment, is proposed for use with this method and with conventional filter coefficient design programs. Filter design from specifications to the structure of Verilog-HDL has been automated. It is possible for a system designer to quickly perform filter LSI optimization by balancing cost and performance.

This paper will describe an overview on several design issues and solutions for the realization of MPEG2 encoder &decoder LSIs. ULSI technology and video-coding specific design have been able to actualize an MPEG2 encoder &decoder LSI with realtime capability, flexibility and cost effectiveness, though MPEG2 processing at MP＠ML (Main Profile and Main Level) requires an enormous computation power of 10-200 GOPS depending on the motion estimation algorithm and a search range. Video coding processors, whose performance has been enhanced at the rate of one order per 3 years, have reached the performance level required to implement MPEG2 encoding using multiple chip configuration. This has been achieved by a hybrid architecture with video-oriented RISC and hardware engine optimized for coding algorithms. Intensive circuit optimization was carried out for transform coding such as DCT and predictive coding with motion estimation. Now cost effective MPEG2 decoders have begun to penetrate the multimedia market. There are two main design issues. One is the architectural and circuit design which minimizes the silicon area and power dissipation. The other is external DRAM control which makes use of DRAM storage and band width efficiently to reduce the system cost. Also future trends in a deep submicron era will be discussed. A single chip MPEG2 MP＠ML encoder is expected to appear in the 0.25 micron era at the latest. An MPEG2 MP＠ML decoder could be compressed to an area of about 25 mm2.

This paper describes a new, low power 16-bit Digital Signal Processor (DSP). The DSP has a double-speed MAC mechanism, an accelerator for Viterbi decoding, and a block floating section which contribute to lower power consumption. The double-speed MAC can perform two multiply and accumulate operations in one instruction cycle. Since MAC operations are so common in digital signal processing, this mechanism can reduce the average clock frequency of the DSP resulting in lower power consumption. The Viterbi accelerator and block floating circuitry also reduce the clock frequency by minimizing the number of required cycles needed to be executed. The DSP was fabricated using a 0.8 µm CMOS 2-aluminum layer process technology to integrate 644 K transistors on a 9.30 mm9.09 mm die. It can realize an 11.2 kbps VSELP speech CODEC while consuming only 70 mW at 3.5 V Vdd.

In order to ensure the reliability and safety of equipment installed in process lines, it is important that maintenance and management should make efficient use of machine diagnosis techniques. Machine diagnosis by means of acoustic signals has hitherto been beset with difficulty, but there is now a strong demand that new acoustic type diagnosis equipment (utilizing acoustic signals) be developed. In response to this demand, the authors recently conducted research on diagnosis of machine faults by means of the processing of acoustic signals. In this research they were able to develop new acoustic type machine diagnosis techniques, and, using these techniques, to develop acoustic diagnosis equipment for practical use.

Efficient retrieval of nested objects is an important issue in advanced database systems. So far, a number of indexing methods for nested objects have been proposed. However, they do not consider retrieval of nested objects based on the set comparison operators such as and . Previouly, we proposed four set access facilities for nested objects and compared their performance in terms of retrieval cost, storage cost, and update cost. In this paper, we extend the study and present refined algorithms and cost formulas applicable to more generalized situations. Our cost models and analysis not only contribute to the study of set-valued retrieval but also to cost estimation of various indexing methods for nested objects in general.

Extremely narrow track width of deep submicron range is examined in perpendicular magnetic recording. Head field distribution of a single-pole head analyzed by 3-dimensional computer simulation results in a sharp gradient, but relatively large cross-sectional area is required to maintain head field strength. Based on this design concept, a lateral single-pole head is described and proved to attain track width of 0.4 µm. In addition, multilevel partial response appropriate to the new multitrack recording system is proposed.

Conventional subband ADF's (adaptive digital filters) using filter banks have shown a degradation in performance because of the non-ideal nature of filters. To solve this problem, we propose a new type of subband ADF incorporating two types of analysis filter bank. In this paper, we show that we can design the optimum filter bank which minimizes the LMSE (least mean squared error). In other words, we can design a subband ADF with less MSE than that of conventional subband ADF's.

This paper deals with the improvement of performance in the transform and subband image coding systems with negatively-correlated input signal. Using a more general source model than the AR(1) model as an input, the coding performance for the transform and subband coding schemes is evaluated in terms of the coding gain over PCM. The source model used here has such resonant band characteristics that its power spectrum has a peak at some frequency between 0 and π/2 for positive autocorrelation and between π/2 and π for negative autocorrelation. It is shown that coding schemes are classified into two classes; one has the pairwise mirror-image property in their filter banks and performs symmetrically regardless of the sign of the autocorrelation, and the other has no that property and performs asymmetrically with inferior performance for negative autocorrelation. Among the well-known transform and subband coding schemes, the DHT and QMF coding systems belong to the former class and the DCT and SSKF coding systems to the latter. In order to remedy the inferior performance, we propose the method in which one modulates the negatively-correlated signal sequences by the alternating sign signal with unity magnitude (-1)n to convert them into positively-correlated sequences. The algorithms are presented for the DCT and SSKF image coding systems with the adaptive signal modulation. In the DCT coding systems, we are particularly concerned with the DCT-based hierarchical progressive coding mode of operation, since the signal modulation works well for that coding mode. The SSKF image coding system has the regular quad-tree structure with three stages. The simulation results for test images show that our method can successfully be applied to the images with a considerable amount of energy in the frequency range higher than π/2 in horizontal or vertical direction, such as fingerprints and textile patterns sampled at a rate close to the Nyquist rate. The paper closes with a brief introduction to the modification of our DCT-based method.

In this paper, an approach to derive a logic function of asynchronous circuits from a graph-based model called Signal Transition Graphs (STG) is discussed. STG's are Petri nets, whose transitions are interpreted as a signal transition on the circuit inputs or gate outputs, and its marking represents a binary state of the circuit. STG's can represent a behavior of circuit, to derive logic functions, however, the reachability graph should be constructed. In the verification of STG's some method based on Occurrence nets (OCN) and its prefix, called unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating substate space of a given STG using the structural properties of OCN. The proposed method can be seem as a parallel algorithm for deriving a logic function.

Currently, many efforts are underway to design wideband mobile communication system. The system is one of alternative of Future Public Land Mobile Telecommunication Systems (FPLMTS). In this paper, we clarify received signal level characteristics for wideband mobile radio channels in line-of-sight (LOS) microcells. The results from urban-area field experiments, where received signal levels for various receiver bandwidths and power delay profiles were measured, show that the depth of fading of the-received signal decreases as normalized RMS delay spread, defined as the product of receiver bandwidth and RMS delay spread, increases. These results are useful in designing wideband microcell systems for urban areas.

When signal subspace techniques, such as MuSIC, are used to locate a number of incident signals, an exhaustive search of the array manifold has to be carried out. This search involves the evaluation of a single cost function at a number of points which form a grid, resulting in quantization-error effects. In this paper a new algorithm is put forward to overcome the quantization problem. The algorithm uses a number of cost functions, and stages, equal to the number of incident signals. At each stage a new cost function is evaluated in a small number of "special" directions, known as characteristic points. For an N-element array the characteristic points, which can be pre-calculated from the array manifold curvatures, partition the array manifold into N-1 regions. By using a simple gradient algorithm, only a small area of one of these regions is searched at each stage, demonstrating the potential benefits of the proposed approach.

Single-reference and multi-reference noise canceller (SRNC and MRNC) performances are investigated based on correlation between signal and noise. Exact relations between these noise canceller performances and signal-noise correlation have not been well discussed yet. In this paper, the above relations are investigated based on theoretical, analysis and computer simulation. The normalized LMS (NLMS) algorithm is employed. Uncorrelate, partially correlated, and correlated signal and noise combinations are taken into account. Computer simulation is carried out, using real speech, white noise, real noise sound, sine wave signals, and their combinations. In the SRNC problem, spectral analysis is applied to derive the canceller output power spectrum. From the simulation results, it is proven that the SRNC performance is inversely proportional to the signal-noise correlation as expected by the theoretical analysis. From the simulation results, the MRNC performance is more sensitive to the signal-noise correlation than that of SRNC. When the signal-noise correlation is high, by using a larger number of adaptive filter taps, the noise is reduced more, and, the signal distortion is increased. This means the signal components included in the noise are canceled exactly.

One of the major open issues in neural network research includes a Network Designing Problem (NDP): find a polynomial-time procedure that produces minimal structures (the minimum intermediate size, thresholds and synapse weights) of multilayer threshold feed-forward networks so that they can yield outputs consistent with given sample sets of input-output data. The NDP includes as a sub-problem a Network Training Problem (NTP) where the intermediate size is given. The NTP has been studied mainly by use of iterative algorithms of network training. This paper, making use of both rate distortion theory in information theory and linear algebra, solves the NDP mathematically rigorously. On the basis of this mathematical solution, it furthermore develops a mathematical solution Procedure to the NDP that computes the minimal structure straightforwardly from the sample set. The Procedure precisely attains the minimum intermediate size, although its computational time complexity can be of non-polynomial order at worst cases. The paper also refers to a polynomial-time shortcut to the Procedure for practical use that can reach an approximately minimum intermediate size with its error measurable. The shortcut, when the intermediate size is pre-specified, reduces to a promising alternative as well to current network training algorithms to the NTP.

In this paper, a new switched-current auto-tuning filter is proposed. Switched-current (SI) is a current-mode analog sampled-data circuit technique. An SI circuit can be realized using only standard digital CMOS technologies, and is capable of realizing high frequency circuits. The proposed filter is composed of SI-OTA (operational transconductance amplifier) integrators. The gain of an SI-OTA integrator can be electronically controlled by the bias current. The proposed filter is a current controlled filter (CCF) and a PLL technique was used as its tuning method. A 2nd-order SI auto-tuning low-pass filter with 100kHz cutoff frequency was designed assuming a 2µm CMOS process. The characteristics of this SI filter and its tuning characteristics were confirmed by SPICE simulations.

The main purpose of this paper is to give a new representation method of the convergence characteristics of the LMS algorithm using tap-input vectors. The described representation method is an extended version of the interpretation method based on the orthogonal projection. Using this new representation, we can express the convergence characteristics in terms of tap-input vectors instead of the eigenvalues of the input signal. From this representation, we consider a general method for improving the convergence speed.

High speed GaAs ICs (Integrated Circutis) using FETs (Field Effect Transistors) are reported. As the fabricating techniques, ion implantation processes for both 0.5 µm and 0.2 µm gate FETs using W/Al refractory metal and 0.2 µm recessed gate process with MBE grown epitaxial wafers are shown. These fabrication processes are selected depending on the circuit speed and the integration level. The outline of the circuit design and the examples of ICs, which are developed for 10 Gb/s optical communication systems, are also shown with the obtained characteristics.

This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.