The high-speed and low-power system LSIs in recent years have crucial need for managing power supply noise so that it might not substantially affect the circuit functionality and performance. The decoupling capacitance is known as an effective measure for suppressing the power supply noise. In this paper, we propose a design methodology for decoupling capacitance budgeting, in which the decoupling capacitance is distributed appropriately over the LSI chip area in order to suppress the power supply noise of each local region. For efficient budgeting, we introduced a new concept of power-capacitance ratio, which is the ratio of power dissipation to capacitance. The proposed method first performs a simplified power supply noise analysis by using a lumped circuit model to determine the total required on-chip capacitance, and calculate the power-capacitance ratio. Then, in the layout design phase, the decoupling capacitance budgeting is performed by using the above power-capacitance ratio as a guideline. The effectiveness of the proposed method was verified by using SPICE simulations on example chip models of 90 nm technology node. The verification results show that, even for a chip with very wide on-chip variation in power density, the proposed method can suppress the power supply noise of each local region effectively.

Three-dimensional integrated circuits (3-D ICs), i.e., stacked dies, can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogenous integration. The vertical connection, which is generally implemented by the through-the-silicon via, is a key technology for 3-D ICs. In this paper, given 3-D circuit placement or floorplan results with white space reserved between blocks for inter-layer interconnections, we proposed methods for assigning inter-layer signal via locations. Introducing a grid structure on the chip, the inter-layer via assignment of two-layer chips can be optimally solved by a convex-cost max-flow formulation with signal via congestion optimized. As for 3-D ICs with three or more layers, the inter-layer signal via assignment is modeled as an integral min-cost multi-commodity flow problem, which is solved by a heuristic method based on the lagrangian relaxation. Relaxing the capacity constraints in the grids, we transfer the min-cost multi-commodity flow problem to a sequence of lagrangian sub-problems, which are solved by finding a sequence of shortest paths. The complexity of solving a lagrangian sub-problem is O(nntng2), where nnt is the number of nets and ng is the number of grids on one chip layer. The experimental results demonstrated the effectiveness of the method.

This paper presents a cache way enabling mechanism using branch target addresses. This mechanism uses branch prediction information to avoid the power consumption due to unnecessary cache way access by enabling only the cache way(s) that should be accessed. The proposed cache way enabling mechanism reduces the power consumption of the instruction cache by 63% without any performance degradation of the processor. An ARM1136 processor simulator and the Synopsys PrimeTime are used to perform the performance/power simulation and static timing analysis of the proposed mechanisms respectively.

It is essential, as bandwidths of wireless communications get wider, to evaluate the imbalances among quadrature mixer ports, in terms of carrier phase offset, IQ gain imbalance, and IQ skew. Because it is time consuming to separate skew, gain imbalance and carrier phase offset evaluation during test is often performed using a composite value, without separation of the imbalance factors. This paper describes an algorithm for enabling separation among quadrature mixer gain imbalance, carrier phase offset, and skew. Since the test time is reduced by the proposed method, it can be applied during high volume production testing.

A new analog mismatch model in circuit level has been developed. MOS transistor's small signal parameters are modeled in term of their matching character for both strong- and weak-inversion operations. Mismatch analysis on basic CMOS amplifiers are conducted with proposed model and Monte Carlo SPICE simulations. We successfully derived simple analytical formula on performance mismatch for analog CMOS circuits, which is verified to be accurate in using actual analog circuit design, within an average error of less than 10%.

A deep submicron semiconductor technology has increased process variations. This fact makes the estimate of the worst-case design margin difficult. In order to realize robust designs, we are investigating such a typical-case design methodology, which we call Constructive Timing Violation (CTV). In the CTV-based design, we can relax timing constraints. However, relaxing timing constraints might cause some timing errors. While we have applied the CTV-based design to a processor, unfortunately, the timing error recovery has serious impact on processor performance. In this paper, we investigate enhancement techniques of the CTV-based design. In addition, in order to accurately evaluate the CTV-based design, we build a co-simulation framework to consider circuit delay at the architectural level. From the co-simulation results, we find the performance penalty is significantly reduced by the enhancement techniques.

This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.

For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. This paper treats the hold constraint in a datapath circuit, and discusses a register assignment in high level synthesis considering delay variations. Our approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). One of our contributions is to show that the minimization of the number of minimum-path delay compensated FUs is NP-hard in general, and it is in the class P if the number of FUs is a constant. A polynomial time algorithm for the latter is also shown in this paper. In addition, an integer linear programming (ILP) formulation is also presented. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.

In this letter, we propose a computationally efficient search space for QRM-MLD that is used for spatially multiplexed multiple antenna systems. We perform a set of computer simulations to show that the proposed method achieves a performance that is near to that of the original QRM-MLD, while its computational complexity is near to that of rank-QRM-MLD.

We address the issue of MIMO channel estimation with the aid of a priori temporal correlation statistics of the channel as well as the spatial correlation. The temporal correlations are incorporated to the estimation scheme by assuming the Gauss-Markov channel model. Under the MMSE criteria, the Kalman filter performs an iterative optimal estimation. To take advantage of the enhanced estimation capability, we focus on the problem of channel estimation from a partial channel measurement in the MIMO antenna selection system. We discuss the optimal training sequence design, and also the optimal antenna subset selection for channel measurement based on the statistics. In a highly correlated channel, the estimation works even when the measurements from some antenna elements are omitted at each fading block.

An algorithm for blind signal separation (BSS) of convolutive mixtures is presented. In this algorithm, the BSS problem is treated as multidimensional independent component analysis (ICA) by introducing an extended signal vector which is composed of current and previous samples of signals. It is empirically known that a number of conventional ICA algorithms solve the multidimensional ICA problem up to permutation and scaling of signals. In this paper, we give theoretical justification for using any conventional ICA algorithm. Then, we discuss the remaining problems, i.e., permutation and scaling of signals. To solve the permutation problem, we propose a simple algorithm which classifies the signals obtained by a conventional ICA algorithm into mutually independent subsets by utilizing temporal structure of the signals. For the scaling problem, we prove that the method proposed by Koldovský and Tichavský is theoretically proper in respect of estimating filtered versions of source signals which are observed at sensors.

This paper proposes a pilot-based channel state information (CSI) feedback from a terminal to a base station (BS), considering the terminal's co-channel interference in a time-division duplex/multi-input multi-output system. In the proposed method, the terminal determines a precoding matrix according to the terminal's co-channel interference characteristics and transmits the precoded pilot signals on uplink. Using the responses of the precoded pilot signals, the BS determines appropriate weight vectors for downlink transmit beams considering the terminal's interference characteristics. Furthermore, the BS can predict the terminal's output signal-to-interference-plus-noise power ratio (SINR) for the downlink data stream. Numerical results show that the BS can achieve efficient transmission and accurate SINR prediction using the proposed CSI feedback.

Slotted wireless ad hoc networks are drawing more and more attention because of their advantage of QoS (Quality of Service) support for multimedia applications owing to their collision-free packet transmission. Time slot assignment is an unavoidable and important problem in such networks. The existing time slot assignment methods have in general a drawback of limited available bandwidth due to their local assignment optimization without the consideration of directions of the radio wave transmission of wireless links along the routes in such networks. A new time slot assignment is proposed in this paper in order to overcome this drawback. The proposed assignment is different from the existing methods in the following aspects: a) consideration of link directions during time slot assignment; b) largest bandwidth to be achieved; c) feasibility in resource limited ad hoc networks because of its fast assignment. Moreover, the effectiveness of the proposal is confirmed by some simulation results.

A method is proposed for estimating code and carrier phase parameters of GNSS reflected signals in low SNR (signal-to-noise ratio) environments. Simulation results show that the multipath impact on code and carrier with 0.022 C/A chips delay can be estimated in 0 dB SNR in the condition of 46 MHz sampling rate.

In some applications, a short private exponent d is chosen to improve the decryption or signing process for RSA public key cryptosystem. However, in a typical RSA, if the private exponent d is selected first, the public exponent e should be of the same order of magnitude as φ(N). Sun et al. devised three RSA variants using unbalanced prime factors p and q to lower the computational cost. Unfortunately, Durfee & Nguyen broke the illustrated instances of the first and third variants by solving small roots to trivariate modular polynomial equations. They also indicated that the instances with unbalanced primes p and q are more insecure than the instances with balanced p and q. This investigation focuses on designing a new RSA variant with balanced p and q, and short exponents d and e, to improve the security of an RSA variant against the Durfee & Nguyen's attack, and the other existing attacks. Furthermore, the proposed variant (Scheme A) is also extended to another RSA variant (Scheme B) in which p and q are balanced, and a trade-off between the lengths of d and e is enable. In addition, we provide the security analysis and feasibility analysis of the proposed schemes.

Two discrete-time Wirtinger-type inequalities relating the power of a finite-length signal to that of its circularly-convolved version are developed. The usual boundary conditions that accompany the existing Wirtinger-type inequalities are relaxed in the proposed inequalities and the equalizing sinusoidal signal is free to have an arbitrary phase angle. A measure of this sinusoidal signal's power, when corrupted with additive noise, is proposed. The application of the proposed measure, calculated as a ratio, in the evaluation of the power of a sinusoid of arbitrary phase with the angular frequency π/N, where N is the signal length, is thoroughly studied and analyzed under additive noise of arbitrary statistical characteristic. The ratio can be used to gauge the power of sinusoids of frequency π/N with a small amount of computation by referring to a ratio-versus-SNR curve and using it to make an estimation of the noise-corrupted sinusoid's SNR. The case of additive white noise is also analyzed. A sample permutation scheme followed by sign modulation is proposed for enlarging the class of target sinusoids to those with frequencies M π/N, where M and N are mutually prime positive integers. Tandem application of the proposed scheme and ratio offers a simple method to gauge the power of sinusoids buried in noise. The generalization of the inequalities to convolution kernels of higher orders as well as the simplification of the proposed inequalities have also been studied.

The process of designing analogue circuits is formulated as a controlled dynamic system. For analysis of such system's properties it is suggested to use the concept of Lyapunov's function for a dynamic system. Various forms of Lyapunov's function are suggested. Analyzing the behavior of Lyapunov's function and its first derivative allowed us to determine significant correlation between this function's properties and processor time used to design the circuit. Numerical results prove the possibility of forecasting the behavior of various designing strategies and processor time based on the properties of Lyapunov's function for the process of designing the circuit.

The wireless systems that establish multiple input multiple output (MIMO) channels through multiple antennas at both ends of the communication link, have been proved to have tremendous potential to linearly lift the capacity of conventional scalar channel. In this paper, we present two efficient decision feedback equalization algorithms that achieve optimal and suboptimal detection order in MIMO spatial multiplexing systems. The new algorithms combine the recursive matrix inversion and ordered QR decomposition approaches, which are developed for nulling cancellation interaface Bell Labs layered space time (BLAST) and back substitution interface BLAST. As a result, new algorithms achieve total reduced complexities in frame based transmission with various payload lengths compared with the earlier methods. In addition, they enable shorter detection delay by carrying out a fast hybrid preprocessing. Moreover, the operation precision insensitivity of order optimization greatly relaxes the word length of matrix inversion, which is the most computational intensive part within the MIMO detection task.

In this letter, we present an exact analytic expression for the maximum signal-to-interference ratio (SIR) for receivers communicating with multiple transmitting nodes over a general time-varying channel, where one of the nodes is chosen as a desired signal source based on the instantaneous channel condition and the other nodes act as interference sources. As an illustrative example, the maximum SIR distribution of a mobile receiver surrounded by three base stations (BS) is determined in a closed-form formula for Rayleigh fading channels, and its accuracy is confirmed using simulation results.

As a method to realize a high-speed communication in the home network, the power-line communication (PLC) technique is known. A problem of PLC is that leakage radiation interferes with existing systems. When OFDM is used in a PLC system, the leakage radiation is not sufficiently reduced, even if the subcarriers corresponding to the frequency-band of the existing system are never used, because the signal is not strictly band-limited. To solve this problem, each subcarrier must be band-limited. In this paper, we apply the OQAM based multi-carrier transmission (OQAM-MCT) to a high-speed PLC system, where each subcarrier is individually band-limited. We also propose a pilot-symbol sequence suitable for frequency offset estimation, symbol-timing detection and channel estimation in the OQAM-MCT system. In this method, the pilot signal-sequence consists of a repeated series of the same data symbol. With this method, the pilot sequence approximately becomes equivalent to OFDM sequence and therefore existing pilot-assisted methods for OFDM are also applicable to OQAM-MCT system. Computer simulation results show that the OQAM-MCT system achieves both good transmission rate performance and low out-of-band radiation in PLC channels. It is also shown that the proposed pilot-sequence improves frequency offset estimation, symbol-timing detection and channel estimation performance as compared with the case of using pseudo-noise sequence.