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1161-1180hit(2667hit)

  • Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems

    Hamid NOORI  Maziar GOUDARZI  Koji INOUE  Kazuaki MURAKAMI  

     
    PAPER

      Vol:
    E91-C No:4
      Page(s):
    418-431

    Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for 40% or more of the total energy consumed in these systems. Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of digital systems continues to grow. Moreover, temperature is another factor that exponentially increases the leakage current. In this paper, we show the effect of temperature on the optimal (minimum-energy-consuming) cache configuration for low energy embedded systems. Our results show that for a given application and technology, the optimal cache size moves toward smaller caches at higher temperatures, due to the larger leakage. Consequently, a Temperature-Aware Configurable Cache (TACC) is an effective way to save energy in finer technologies when the embedded system is used in different temperatures. Our results show that using a TACC, up to 61% energy can be saved for instruction cache and 77% for data cache compared to a configurable cache that has been configured for only the corner-case temperature (100). Furthermore, the TACC also enhances the performance by up to 28% for the instruction cache and up to 17% for the data cache.

  • Optimization for Optical Network Designs Based on Existing Power Grids

    Areeyata SRIPETCH  Poompat SAENGUDOMLERT  

     
    PAPER-Optical Fiber for Communications

      Vol:
    E91-B No:3
      Page(s):
    689-699

    In a power grid used to distribute electricity, optical fibers can be inserted inside overhead ground wires to form an optical network infrastructure for data communications. Dense wavelength division multiplexing (DWDM)-based optical networks present a promising approach to achieve a scalable backbone network for power grids. This paper proposes a complete optimization procedure for optical network designs based on an existing power grid. We design a network as a subgraph of the power grid and divide the network topology into two layers: backbone and access networks. The design procedure includes physical topology design, routing and wavelength assignment (RWA) and optical amplifier placement. We formulate the problem of topology design into two steps: selecting the concentrator nodes and their node members, and finding the connections among concentrators subject to the two-connectivity constraint on the backbone topology. Selection and connection of concentrators are done using integer linear programming (ILP). For RWA and optical amplifier placement problem, we solve these two problems together since they are closely related. Since the ILP for solving these two problems becomes intractable with increasing network size, we propose a simulated annealing approach. We choose a neighborhood structure based on path-switching operations using k shortest paths for each source and destination pair. The optimal number of optical amplifiers is solved based on local search among these neighbors. We solve and present some numerical results for several randomly generated power grid topologies.

  • Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors

    Masato NAKAZATO  Michiko INOUE  Satoshi OHTAKE  Hideo FUJIWARA  

     
    PAPER-High-Level Testing

      Vol:
    E91-D No:3
      Page(s):
    763-770

    In this paper, we propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency, that is, it completely avoids the error masking. Moreover, the proposed method has no performance degradation (adds only observation points) and enables at-speed testing.

  • RSFQ Baseband Digital Signal Processing

    Anna Yurievna HERR  

     
    INVITED PAPER

      Vol:
    E91-C No:3
      Page(s):
    293-305

    Ultra fast switching speed of superconducting digital circuits enable realization of Digital Signal Processors with performance unattainable by any other technology. Based on rapid-single-flux technology (RSFQ) logic, these integrated circuits are capable of delivering high computation capacity up to 30 GOPS on a single processor and very short latency of 0.1 ns. There are two main applications of such hardware for practical telecommunication systems: filters for superconducting ADCs operating with digital RF data and recursive filters at baseband. The later of these allows functions such as multiuser detection for 3G WCDMA, equalization and channel precoding for 4G OFDM MIMO, and general blind detection. The performance gain is an increase in the cell capacity, quality of service, and transmitted data rate. The current status of the development of the RSFQ baseband DSP is discussed. Major components with operating speed of 30 GHz have been developed. Designs, test results, and future development of the complete systems including cryopackaging and CMOS interface are reviewed.

  • Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints

    Thomas Edison YU  Tomokazu YONEDA  Danella ZHAO  Hideo FUJIWARA  

     
    PAPER-Dependable Computing

      Vol:
    E91-D No:3
      Page(s):
    807-814

    The rapid advancement of VLSI technology has made it possible for chip designers and manufacturers to embed the components of a whole system onto a single chip, called System-on-Chip or SoC. SoCs make use of pre-designed modules, called IP-cores, which provide faster design time and quicker time-to-market. Furthermore, SoCs that operate at multiple clock domains and very low power requirements are being utilized in the latest communications, networking and signal processing devices. As a result, the testing of SoCs and multi-clock domain embedded cores under power constraints has been rapidly gaining importance. In this research, a novel method for designing power-aware test wrappers for embedded cores with multiple clock domains is presented. By effectively partitioning the various clock domains, we are able to increase the solution space of possible test schedules for the core. Since previous methods were limited to concurrently testing all the clock domains, we effectively remove this limitation by making use of bandwidth conversion, multiple shift frequencies and properly gating the clock signals to control the shift activity of various core logic elements. The combination of the above techniques gains us greater flexibility when determining an optimal test schedule under very tight power constraints. Furthermore, since it is computationally intensive to search the entire expanded solution space for the possible test schedules, we propose a heuristic 3-D bin packing algorithm to determine the optimal wrapper architecture and test schedule while minimizing the test time under power and bandwidth constraints.

  • Advances in High-Tc Single Flux Quantum Device Technologies

    Keiichi TANABE  Hironori WAKANA  Koji TSUBONE  Yoshinobu TARUTANI  Seiji ADACHI  Yoshihiro ISHIMARU  Michitaka MARUYAMA  Tsunehiro HATO  Akira YOSHIDA  Hideo SUZUKI  

     
    INVITED PAPER

      Vol:
    E91-C No:3
      Page(s):
    280-292

    We have developed the fabrication process, the circuit design technology, and the cryopackaging technology for high-Tc single flux quantum (SFQ) devices with the aim of application to an analog-to-digital (A/D) converter circuit for future wireless communication and a sampler system for high-speed measurements. Reproducibility of fabricating ramp-edge Josephson junctions with IcRn products above 1 mV at 40 K and small Ic spreads on a superconducting groundplane was much improved by employing smooth multilayer structures and optimizing the junction fabrication process. The separated base-electrode layout (SBL) method that suppresses the Jc spread for interface-modified junctions in circuits was developed. This method enabled low-frequency logic operations of various elementary SFQ circuits with relatively wide bias current margins and operation of a toggle-flip-flop (T-FF) above 200 GHz at 40 K. Operation of a 1:2 demultiplexer, one of main elements of a hybrid-type Σ-Δ A/D converter circuit, was also demonstrated. We developed a sampler system in which a sampler circuit with a potential bandwidth over 100 GHz was cooled by a compact stirling cooler, and waveform observation experiments confirmed the actual system bandwidth well over 50 GHz.

  • Optimum Pulse Shape Design for UWB Systems with Timing Jitter

    Wilaiporn LEE  Suwich KUNARUTTANAPRUK  Somchai JITAPUNKUL  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E91-B No:3
      Page(s):
    772-783

    This paper proposes a novel technique in designing the optimum pulse shape for ultra wideband (UWB) systems under the presence of timing jitter. In the UWB systems, pulse transmission power and timing jitter tolerance are crucial keys to communications success. While there is a strong desire to maximize both of them, one must be traded off against the other. In the literature, much effort has been devoted to separately optimize each of them without considering the drawback to the other. In this paper, both factors are jointly considered. The proposed pulse attains the adequate power to survive the noise floor and at the same time provides good resistance to the timing jitter. The proposed pulse also meets the power spectral mask restriction as prescribed by the Federal Communications Commission (FCC) for indoor UWB systems. Simulation results confirm the advantages of the proposed pulse over other previously known UWB pulses. Parameters of the proposed optimization algorithm are also investigated in this paper.

  • Robust F0 Estimation Using ELS-Based Robust Complex Speech Analysis

    Keiichi FUNAKI  Tatsuhiko KINJO  

     
    LETTER-Digital Signal Processing

      Vol:
    E91-A No:3
      Page(s):
    868-871

    Complex speech analysis for an analytic speech signal can accurately estimate the spectrum in low frequencies since the analytic signal provides spectrum only over positive frequencies. The remarkable feature makes it possible to realize more accurate F0 estimation using complex residual signal extracted by complex-valued speech analysis. We have already proposed F0 estimation using complex LPC residual, in which the autocorrelation function weighted by AMDF was adopted as the criterion. The method adopted MMSE-based complex LPC analysis and it has been reported that it can estimate more accurate F0 for IRS filtered speech corrupted by white Gauss noise although it can not work better for the IRS filtered speech corrupted by pink noise. In this paper, robust complex speech analysis based on ELS (Extended Least Square) method is introduced in order to overcome the drawback. The experimental results for additive white Gauss or pink noise demonstrate that the proposed algorithm based on robust ELS-based complex AR analysis can perform better than other methods.

  • Underwater Transient Signal Classification Using Binary Pattern Image of MFCC and Neural Network

    Taegyun LIM  Keunsung BAE  Chansik HWANG  Hyeonguk LEE  

     
    LETTER-Engineering Acoustics

      Vol:
    E91-A No:3
      Page(s):
    772-774

    This paper presents a new method for classification of underwater transient signals, which employs a binary image pattern of the mel-frequency cepstral coefficients as a feature vector and a feed-forward neural network as a classifier. The feature vector is obtained by taking DCT and 1-bit quantization for the square matrix of the mel-frequency cepstral coefficients that is derived from the frame based cepstral analysis. The classifier is a feed-forward neural network having one hidden layer and one output layer, and a back propagation algorithm is used to update the weighting vector of each layer. Experimental results with underwater transient signals demonstrate that the proposed method is very promising for classification of underwater transient signals.

  • Filtering in Generalized Signal-Dependent Noise Model Using Covariance Information

    Seiichi NAKAMORI  María J. GARCIA-LIGERO  Aurora HERMOSO-CARAZO  Josefa LINARES-PEREZ  

     
    PAPER-Digital Signal Processing

      Vol:
    E91-A No:3
      Page(s):
    809-817

    In this paper, we propose a recursive filtering algorithm to restore monochromatic images which are corrupted by general dependent additive noise. It is assumed that the equation which describes the image field is not available and a filtering algorithm is obtained using the information provided by the covariance functions of the signal, noise that affects the measurement equation, and the fourth-order moments of the signal. The proposed algorithm is obtained by an innovation approach which provides a simple derivation of the least mean-squared error linear estimators. The estimation of the grey level in each spatial coordinate is made taking into account the information provided by the grey levels located on the row of the pixel to be estimated. The proposed filtering algorithm is applied to restore images which are affected by general signal-dependent additive noise.

  • Multichannel Linear Prediction Method Compliant with the MPEG-4 ALS

    Yutaka KAMAMOTO  Noboru HARADA  Takehiro MORIYA  

     
    PAPER-Audio Coding

      Vol:
    E91-A No:3
      Page(s):
    756-762

    A new linear prediction analysis method for multichannel signals was devised, with the goal of enhancing the compression performance of the MPEG-4 Audio Lossless Coding (ALS) compliant encoder and decoder. The multichannel coding tool for this standard carries out an adaptively weighted subtraction of the residual signals of the coding channel from those of the reference channel, both of which are produced by independent linear prediction. Our linear prediction method tries to directly minimize the amplitude of the predicted residual signal after subtraction of the signals of the coding channel, and the method has been implemented in the MPEG-4 ALS codec software. The results of a comprehensive evaluation show that this method reduces the size of a compressed file. The maximum improvement of the compression ratio is 14.6% which is achieved at the cost of a small increase in computational complexity at the encoder and without increase in decoding time. This is a practical method because the compressed bitstream remains compliant with the MPEG-4 ALS standard.

  • A Sparse Decomposition Method for Periodic Signal Mixtures

    Makoto NAKASHIZUKA  

     
    PAPER-Digital Signal Processing

      Vol:
    E91-A No:3
      Page(s):
    791-800

    This study proposes a method to decompose a signal into a set of periodic signals. The proposed decomposition method imposes a penalty on the resultant periodic subsignals in order to improve the sparsity of decomposition and avoid the overestimation of periods. This penalty is defined as the weighted sum of the l2 norms of the resultant periodic subsignals. This decomposition is approximated by an unconstrained minimization problem. In order to solve this problem, a relaxation algorithm is applied. In the experiments, decomposition results are presented to demonstrate the simultaneous detection of periods and waveforms hidden in signal mixtures.

  • Linear Discriminant Analysis Using a Generalized Mean of Class Covariances and Its Application to Speech Recognition

    Makoto SAKAI  Norihide KITAOKA  Seiichi NAKAGAWA  

     
    PAPER-Feature Extraction

      Vol:
    E91-D No:3
      Page(s):
    478-487

    To precisely model the time dependency of features is one of the important issues for speech recognition. Segmental unit input HMM with a dimensionality reduction method has been widely used to address this issue. Linear discriminant analysis (LDA) and heteroscedastic extensions, e.g., heteroscedastic linear discriminant analysis (HLDA) or heteroscedastic discriminant analysis (HDA), are popular approaches to reduce dimensionality. However, it is difficult to find one particular criterion suitable for any kind of data set in carrying out dimensionality reduction while preserving discriminative information. In this paper, we propose a new framework which we call power linear discriminant analysis (PLDA). PLDA can be used to describe various criteria including LDA, HLDA, and HDA with one control parameter. In addition, we provide an efficient selection method using a control parameter without training HMMs nor testing recognition performance on a development data set. Experimental results show that the PLDA is more effective than conventional methods for various data sets.

  • Signal Processing Techniques for Robust Speech Recognition

    Futoshi ASANO  

     
    INVITED PAPER

      Vol:
    E91-D No:3
      Page(s):
    393-401

    In this paper, signal processing techniques which can be applied to automatic speech recognition to improve its robustness are reviewed. The choice of signal processing techniques is strongly dependent on the scenario of the applications. The analysis of scenario and the choice of suitable signal processing techniques are shown through two examples.

  • A Low-Noise Amplifier for WCDMA Terminal with High Tolerance for Leakage Signal from Transmitter

    Ryuichi FUJIMOTO  Gaku TAKEMURA  Masato ISHII  Takehiko TOYODA  Hiroshi TSURUMI  

     
    PAPER

      Vol:
    E91-A No:2
      Page(s):
    521-528

    Since a receiver (RX) and a transmitter (TX) are operated simultaneously in a WCDMA transceiver, noise and intermodulation distortion performances of a low-noise amplifier (LNA) are degraded by a large leakage signal from the TX. The degradation of the distortion due to the large leakage signal from the TX has been reported in some previous works, but to our best knowledge, there are no reports about the degradation of noise figure (NF) in a LNA due to the large leakage signal from the TX. In this paper, a 900-MHz LNA for WCDMA terminal with high tolerance for a leakage signal from the TX is proposed. Suitable designs of an input matching circuit and a trap circuit are adopted to improve the tolerance for the leakage signal from the TX. The LNA using the proposed techniques is fabricated using SiGe-BiCMOS process. The measured degradation of NF due to the leakage signal from the TX is suppressed to only 0.12 dB.

  • Channel Estimation with a New Preamble Structure for a MIMO OFDM-Based WLAN System

    Jihyung KIM  Sangho NAM  Dongjun LEE  Jonghan KIM  Jongae PARK  Daesik HONG  

     
    LETTER-Wireless Communication Technologies

      Vol:
    E91-B No:2
      Page(s):
    649-652

    In this letter, we propose a new preamble structure for channel estimation in a MIMO OFDM-based WLAN system. Both backward compatibility with IEEE 802.11a and low overhead are considered in designing the preamble. Simulation results show that the proposed preamble has low overhead and good performance gain for channel estimation.

  • A Note on the Random Oracle Methodology

    Mototsugu NISHIOKA  Naohisa KOMATSU  

     
    PAPER-Cryptography and Information Security

      Vol:
    E91-A No:2
      Page(s):
    650-663

    Canetti et al. [5] showed that there exist signature and encryption schemes that are secure in the random oracle (RO) model, but for which any implementation of the RO (by a single function or a function ensemble) results in insecure schemes. Their result greatly motivates the design of cryptographic schemes that are secure in the standard computational model. This paper gives some new results on the RO methodology. First, we give the necessary and sufficient condition for the existence of a signature scheme that is secure in the RO model but where, for any implementation of the RO, the resulting scheme is insecure. Next, we show that this condition induces a signature scheme that is insecure in the RO model, but that there is an implementation of the RO that makes the scheme secure.

  • Mobility Prediction Progressive Routing (MP2R), a Cross-Layer Design for Inter-Vehicle Communication

    Suhua TANG  Naoto KADOWAKI  Sadao OBANA  

     
    PAPER-Network

      Vol:
    E91-B No:1
      Page(s):
    221-231

    In this paper we analyze the characteristics of vehicle mobility and propose a novel Mobility Prediction Progressive Routing (MP2R) protocol for Inter-Vehicle Communication (IVC) that is based on cross-layer design. MP2R utilizes the additional gain provided by the directional antennas to improve link quality and connectivity; interference is reduced by the directional transmission. Each node learns its own position and speed and that of other nodes, and performs position prediction. (i) With the predicted progress and link quality, the forwarding decision of a packet is locally made, just before the packet is actually transmitted. In addition the load at the forwarder is considered in order to avoid congestion. (ii) The predicted geographic direction is used to control the beam of the directional antenna. The proposed MP2R protocol is especially suitable for forwarding burst traffic in highly mobile environments. Simulation results show that MP2R effectively reduces Packet Error Ratio (PER) compared with both topology-based routing (AODV [1], FSR [2]) and normal progressive routing (NADV [18]) in the IVC scenarios.

  • Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's

    Doo-Hwan KIM  Sung-Hyun YANG  Kyoung-Rok CHO  

     
    PAPER-Electronic Circuits

      Vol:
    E91-C No:1
      Page(s):
    72-80

    This paper proposes a dual-level low voltage differential signaling (DLVDS) circuit aimed at low power consumption and reducing transmission lines for LCD driver IC's. We apply two-bit binary data to the DLVDS circuit as inputs, and then the circuit converts these two inputs into two kinds of fully differential signal levels. In the DLVDS circuit, two transmission lines are sufficient to transfer two-bit binary inputs while keeping the conventional LVDS features. The receiver recovers the original two-bit binary data through a level decoding circuit. The proposed circuit was fabricated using a commercial 0.25 µm CMOS technology. Under a 2.5 V supply voltage, the circuit shows a data rate of 1-Gbps/2-line and power consumption of 35 mW.

  • General Conversion for Obtaining Strongly Existentially Unforgeable Signatures

    Isamu TERANISHI  Takuro OYAMA  Wakaha OGATA  

     
    PAPER-Signatures

      Vol:
    E91-A No:1
      Page(s):
    94-106

    We say that a signature scheme is strongly existentially unforgeable (SEU) if no adversary, given message/signature pairs adaptively, can generate a signature on a new message or a new signature on a previously signed message. We propose a general and efficient conversion in the standard model that transforms a secure signature scheme to SEU signature scheme. In order to construct that conversion, we use a chameleon commitment scheme. Here a chameleon commitment scheme is a variant of commitment scheme such that one can change the committed value after publishing the commitment if one knows the secret key. We define the chosen message security notion for the chameleon commitment scheme, and show that the signature scheme transformed by our proposed conversion satisfies the SEU property if the chameleon commitment scheme is chosen message secure. By modifying the proposed conversion, we also give a general and efficient conversion in the random oracle model, that transforms a secure signature scheme into a SEU signature scheme. This second conversion also uses a chameleon commitment scheme but only requires the key only attack security for it.

1161-1180hit(2667hit)