In this letter the complexity of factoring an α-LSBS modulus is analyzed. This gives an improvement on the lower bound of the previous results.

We explicitly describe and analyse blind hierachical identity-based encryption (blind HIBE) schemes, which are natural generalizations of blind IBE schemes [20]. We then uses the blind HIBE schemes to construct: (1) An identity-based blind signature scheme secure in the standard model, under the computational Diffie-Hellman (CDH) assumption, and with much shorter signature size and lesser communication cost, compared to existing proposals. (2) A new mechanism supporting a user to buy digital information over the Internet without revealing what he/she has bought, while protecting the providers from cheating users.

Many DSP applications such as FIR filtering and DCT (discrete cosine transformation) require multiplication with constants. Therefore, optimizing the performance of constant multiplication improves the overall performance of these applications. It is well-known that shifting can replace a constant multiplication if the constant is a power of two. In this paper, we extend this idea in such a way that by employing more than two barrel shifters, we can design highly efficient constant multipliers. We have found that by using two or three shifters, we can generate a large set of constants. Using these constants, we can execute a typical set of FIR or DCT applications with few errors. Furthermore, with variable precision support, we can carry out a fairly large class of DSP applications with high computational efficiency. Compared to conventional multipliers, we can achieve power savings of up to 56% with negligible computational errors.

Optical buffer memory for 10-Gb/s data signal is demonstrated experimentally using a polarization bistable vertical-cavity surface-emitting laser (VCSEL). The optical buffer memory is based on an optical AND gate function and the polarization bistability of the VCSEL. Fast AND gate operation responsive to 50-ps-width optical pulses is achieved experimentally by increasing the detuning frequency between an injection light into the VCSEL and a lasing light from the VCSEL. A specified bit is extracted from the 10-Gb/s data signal by the fast AND gate operation and is stored as the polarization state of the VCSEL by the polarization bistability. The corresponding numerical simulations are also performed using two-mode rate equations taking into account the detuning frequency. The simulation results confirm the fast AND gate operation by increasing the detuning frequency as well as the experimental results.

By modifying the private key and the public key setting in Boneh-Lynn-Shacham's short signature shcheme, a variation of BLS' short signature scheme is proposed. Based on this variation, we present a very efficient threshold signature scheme where the number of pairing computation for the signaure share verification reduces to half.

In this letter, we propose a network-adaptive video streaming scheme based on cross-layered hop-by-hop video rate control in wireless multi-hop networks. We argue that existing end-to-end network-adaptive video rate control schemes, which utilize end-to-end statistics, exhibit serious performance degradation in severely interfered wireless network condition. To cope with this problem, in the proposed scheme, intermediate wireless nodes adjust video sending rate depending upon wireless channel condition measured at MAC (Medium Access Control) layer. Extensive experimental results from an IEEE 802.11a-based testbed show that the proposed scheme improves the perceptual video quality compared to an end-to-end scheme.

This paper presents a grouped scan slice encoding technique using scan slice repetition to simultaneously reduce test data volume and test application time. Using this method, many scan slices that would be incompatible with the conventional selective scan slice method can be encoded as compatible scan slices. Experiments were performed with ISCAS'89 and ITC'99 benchmark circuits, and results show the effectiveness of the proposed method.

This paper proposes an indoor event detection system for homes and offices that is based on electric wave reception such as intrusion into home or office. The proposed system places antenna array on the receiver side and detects events such as intrusion using the eigenvector spanning signal subspace obtained by the antenna array. The eigenvector is based on not received signal strengths (RSS) but direction of arrival (DOA) of incident signals on the antenna array. Therefore, in a static state, the variance of the eigenvector over time is smaller than that of RSS. The eigenvector changes only when the indoor environment of interest changes intermittently and statically, or dynamically. The installation cost is low, because the detection range is wide owing to indoor reflections and diffraction of electric wave and only a pair of transmitter and receiver are used. Experimental results reveal that the proposed method can distinguish the state when no event occurs and that when an event occurs clearly. Since the proposed method has a low false detection rate, it offers higher detection rates than the systems based on RSS.

Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15 pJ/conversion-step.

We propose a new modulation, phase-silence-shift-keying (PSSK), whose symbol error rate (SER) performance is improved by 6 dB compared with phase-shift-keying (PSK). To prove this, theoretical analysis of probability of error is provided and simulation results are presented.

Placing a guard trace next to a signal line is the conventional technique for reducing the common-mode radiation from a printed circuit board. In this paper, the suppression of common-mode radiation from printed circuit boards having guard traces is estimated and evaluated using the imbalance difference model, which was proposed by the authors. To reduce common-mode radiation further, a procedure for designing a transmission line with guard traces is proposed. Guard traces connected to a return plane through vias are placed near a signal line and they decrease a current division factor (CDF). The CDF represents the degree of imbalance of a transmission line, and a common-mode electromotive force depends on the CDF. Thus, by calculating the CDF, we can estimate the reduction in common-mode radiation. It is reduced not only by placing guard traces, but also by narrowing the signal line to compensate for the variation in characteristic impedance due to the guard traces. Experimental results showed that the maximum reduction in common-mode radiation was about 14 dB achieved by placing guard traces on both sides of the signal line, and the calculated reduction agreed with the measured one within 1 dB. According to the CDF and characteristic impedance calculations, common-mode radiation can be reduced by about 25 dB while keeping the characteristic impedance constant by changing the gap between the signal line and the guard trace and by narrowing the width of the signal line.

The key issue in cognitive radio is to design a reliable spectrum sensing method that is able to detect the signal in the target channel as well as to recognize its type. In this paper, focusing on classifying different orthogonal frequency-division multiplexing (OFDM) signals, we propose a two-step detection and identification approach based on the analysis of the cyclic autocorrelation function. The key parameters to separate different OFDM signals are the subcarrier spacing and symbol duration. A symmetric peak detection method is adopted in the first step, while a pulse detection method is used to determine the symbol duration. Simulations validate the proposed method.

Even though it is very important to retrieve similar trajectories with a given query trajectory, there has been a little research on trajectory retrieval in spatial networks, like road networks. In this paper, we propose an efficient indexing scheme for retrieving moving object trajectories in spatial networks. For this, we design a signature-based indexing scheme for efficiently dealing with the trajectories of current moving objects as well as for maintaining those of past moving objects. In addition, we provide an insertion algorithm for storing the segment information of a moving object trajectory as well as a retrieval algorithm to find a set of moving objects whose trajectories match the segments of a query trajectory. Finally, we show that our signature-based indexing scheme achieves at least twice better performance on trajectory retrieval than the leading trajectory indexing schemes, such as TB-tree, FNR-tree, and MON-tree.

In this paper the time-domain analysis of two parallel traces is investigated. First, the telegrapher's equations for transmission line are applied to the parallel traces on printed circuit board (PCB), and are solved by using the mode decomposition technique. The time-domain solutions are then obtained by using the inverse Laplace transform. Although the Fourier-transform technique is also applicable for this problem, the solution is given numerically. Contrarily, the inverse Laplace transform successfully leads to an analytical expression for the transmission characteristics. The analytical expression is represented by series, which clearly explains the coupling mechanism. The analytical expression for the fundamental section of a meander delay line is investigated in detail. The analytical solution is validated by measurements, and the characteristics of the distortions in the output waveforms of meander delay lines due to the crosstalk are also investigated.

Analog multipliers are one of the most important building blocks in analog signal processing circuits. The performance with high linearity and wide input range is usually required for analog four-quadrant multipliers in most applications. Therefore, a highly linear and wide input range four-quadrant CMOS analog multiplier using active feedback is proposed in this paper. Firstly, a novel configuration of four-quadrant multiplier cell is presented. Its input dynamic range and linearity are improved significantly by adding two resistors compared with the conventional structure. Then based on the proposed multiplier cell configuration, a four-quadrant CMOS analog multiplier with active feedback technique is implemented by two operational amplifiers. Because of both the proposed multiplier cell and active feedback technique, the proposed multiplier achieves a much wider input range with higher linearity than conventional structures. The proposed multiplier was fabricated by a 0.6 µm CMOS process. Experimental results show that the input range of the proposed multiplier can be up to 5.6Vpp with 0.159% linearity error on VX and 4.8Vpp with 0.51% linearity error on VY for 2.5V power supply voltages, respectively.

A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-µm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600 MHz and 8.35 µW at a 0.5 V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang's counter [1], and the E-TSPC counter [2], respectively.

In an embedded system where a single application or a class of applications is repeatedly executed on a processor, its cache configuration can be customized such that an optimal one is achieved. We can have an optimal cache configuration which minimizes overall memory access time by varying the three cache parameters: the number of sets, a line size, and an associativity. In this paper, we first propose two cache simulation algorithms: CRCB1 and CRCB2, based on Cache Inclusion Property. They realize exact cache simulation but decrease the number of cache hit/miss judgments dramatically. We further propose three more cache design space exploration algorithms: CRMF1, CRMF2, and CRMF3, based on our experimental observations. They can find an almost optimal cache configuration from the viewpoint of access time. By using our approach, the number of cache hit/miss judgments required for optimizing cache configurations is reduced to 1/10-1/50 compared to conventional approaches. As a result, our proposed approach totally runs an average of 3.2 times faster and a maximum of 5.3 times faster compared to the fastest approach proposed so far. Our proposed cache simulation approach achieves the world fastest cache design space exploration when optimizing total memory access time.

This paper analyzes frequency tracking characteristics of a complex-coefficient adaptive infinite impulse response (IIR) notch filter with a simplified gradient-based algorithm. The input signal to the complex notch filter is a complex linear chirp embedded in a complex zero-mean white Gaussian noise. The analysis starts with derivation of a first-order real-coefficient difference equation with respect to steady-state instantaneous frequency tracking error. Closed-form expression for frequency tracking mean square error (MSE) is then derived from the difference equation. Lastly, closed-form expressions for optimum notch bandwidth coefficient and step size constant that minimize the frequency tracking MSE are derived. Computer simulations are presented to validate the analysis.

Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and a printed circuit board, but it takes much time in manual routing. We propose a fast routing method for 2-layer Ball Grid Array packages that iteratively modifies via assignment. In experiments, in most cases, via assignment and global routing on both of layers in which all nets are realized and the violation of wire congestion on layer 1 is small are speedily obtained.

We describe the applicability of photonic crystal fiber (PCF) with an enlarged effective area Aeff to a distributed Raman amplification (DRA) transmission. We investigate the DRA transmission performance numerically over a large Aeff PCF taking account of the signal-to-noise ratio (SNR) improvement RSNR in the S, C, and L bands. We show that an RSNR of 3 dB can be expected by utilizing DRA with a maximum pump power of 500 mW when the Aeff of the PCF is 230 µm2.