This paper presents a low-power System on Chip (SOC) architecture for the v2.0+EDR (Enhanced Data Rate) Bluetooth and its applications. Our design includes a link controller, modem, RF transceiver, Sub-Band Codec (SBC), Expanded Instruction Set Computer (ESIC) processor, and peripherals. To decrease power consumption of the proposed SOC, we reduce data transfer using a dual-port memory, including a power management unit, and a clock gated approach. We also address some of issues and benefits of reusable and unified environment on a centralized data structure and SOC verification platform. This includes flexibility in meeting the final requirements using technology-independent tools wherever possible in various processes and for projects. The other aims of this work are to minimize design efforts by avoiding the same work done twice by different people and to reuse the similar environment and platform for different projects. This chip occupies a die size of 30 mm2 in 0.18 µm CMOS, and the worst-case current of the total chip is 54 mA.

This paper focuses on the problem of performance degradation in mismatched speech recognition. The F-Ratio analysis method is utilized to analyze the significance of different frequency bands for speech unit classification, and we find that frequencies around 1 kHz and 3 kHz, which are the upper bounds of the first and the second formants for most of the vowels, should be emphasized in comparison to the Mel-frequency cepstral coefficients (MFCC). The analysis result is further observed to be stable in several typical mismatched situations. Similar to the Mel-Frequency scale, another frequency scale called the F-Ratio-scale is thus proposed to optimize the filter bank design for the MFCC features, and make each subband contains equal significance for speech unit classification. Under comparable conditions, with the modified features we get a relative 43.20% decrease compared with the MFCC in sentence error rate for the emotion affected speech recognition, 35.54%, 23.03% for the noisy speech recognition at 15 dB and 0 dB SNR (signal to noise ratio) respectively, and 64.50% for the three years' 863 test data. The application of the F-Ratio analysis on the clean training set of the Aurora2 database demonstrates its robustness over languages, texts and sampling rates.

We present a session initiation protocol (SIP) network design for a voice-over-IP network to prevent congestion caused by people calling friends and family after a disaster. The design increases the capacity of SIP servers in a network by using all of the SIP servers equally. It takes advantage of the fact that equipment for voice data packets is different from equipment for signaling packets in SIP networks. Furthermore, the design achieves simple routing on the basis of telephone numbers. We evaluated the performance of our design in preventing congestion through simulation. We showed that the proposed design has roughly 20 times more capacity, which is 57 times the normal load, than the conventional design if a disaster were to occur in Niigata Prefecture struck by the Chuetsu earthquake in 2004.

This paper studies the performance of a coded convolutional spreading CDMA system with cyclic prefix (CS-CDMA/CP) combined with the zero correlation zone code generated from the M-sequence (M-ZCZ code) for downlink transmission over a multipath fast fading channel. In particular, we propose a new pilot-aided channel estimation scheme based on the shift property of the M-ZCZ code and show the robustness of the scheme against fast fading through comparison with the W-CDMA system empolying time-multiplexed pilot signals.

In this letter, we propose an interference-aware resource allocation algorithm for the uplink of OFDMA systems. It comprises a macrocell overlaid with short range femtocells. We define the interferences that occur between a macrocell and femtocells and present the resource assignment algorithm to resolve and mitigate the cross-tier interference effect based on the defined interference factors. Simulation results show that the proposed algorithm performs well in a macrocell and femtocells.

A unipolar n-n heterostrucuture diode is developed in the InP material system. The electronic barrier is formed by a saw tooth type of conduction band bending which consists of a quaternary In0.52(AlyGa1-y)0.48As layer with 0 < y < ymax. This barrier is lattice matched for all y to InP and is embedded between two n+-InGaAs layers. By varying the maximum Al-content from ymax,1 = 0.7 to ymax,2 = 1 a variable barrier height is formed which enables a diode-type I-V characteristic by epitaxial design with an adjustable current density within 3 orders of magnitude. The high current density of the diode with the lower barrier height (ymax,1 = 0.7) makes it suitable for high frequency applications at low signal levels. RF measurements reveal a speed index of 52 ps/V at VD = 0.15 V. The device is investigated for RF-to-DC power conversion in UHF RFID transponders with low-amplitude RF signals.

This paper proposes a new multi-band received signal strength (MRSS) fingerprinting based indoor location system, which employs the frequency diversity on the conventional single-band received signal strength (RSS) fingerprinting based indoor location system. In the proposed system, the impacts of frequency diversity on the enhancements of positioning accuracy are analyzed. Effectiveness of the proposed system is proved by experimental approach, which was conducted in non line-of-sight (NLOS) environment under the area of 103 m2 at Yagami Campus, Keio University. WLAN access points, which simultaneously transmit dual-band signal of 2.4 and 5.2 GHz, are utilized as transmitters. Likewise, a dual-band WLAN receiver is utilized as a receiver. Signal distances calculated by both Manhattan and Euclidean were classified by K-Nearest Neighbor (KNN) classifier to illustrate the performance of the proposed system. The results confirmed that Frequency diversity attributions of multi-band signal provide accuracy improvement over 50% of the conventional single-band.

A novel construction of complementary sequences with multi-width zero cross-correlation zone (ZCCZ) is presented based on the interleaving iteration of a basic kernel set. The presented multi-width ZCCZ complementary (MWZC) sequences can be divided into multiple sequence groups, the correlation functions of which possess one-width intragroup ZCCZ and multi-width intergroup ZCCZ. When an arbitrary orthogonal sequence set with set size equal to sequence length is used as a basic kernel set, the constructed MWZC sequence set and the combination sets of specific subsets with each subset including several groups can be optimal with respect to the theoretical bound on set size. In addition, the MWZC sequence set includes complementary sequence sets with one-width or two-width ZCCZ as special subsets, and allows a more flexible choice of sequence parameters.

The large signal performance and model for GaN FET devices was evaluated with DC, S-parameters, and large signal measurements. The large signal model was extended with bias and temperature dependence of access resistances, modified capacitance and charge equations, as well as breakdown models. The model was implemented in a commercial CAD tool and exhibits good overall accuracy.

Detection of transient signals is generally done by examining power and spectral variation of the received signal, but it becomes a difficult task when the background noise gets large. In this paper, we propose a robust transient detection algorithm using the EVRC noise suppression module. We define new parameters from the outputs of the EVRC noise suppression module for transient detection. Experimental results with various types of underwater transients have shown that the proposed method outperforms the conventional energy-based method and achieved performance improvement of detection rate by 7% to 15% for various types of background noise.

In this paper, the transmission and reflection properties of the microstrip line with bends are investigated using the Fourier transform and a mode-matching technique. Based on the waveguide model, the microstrip bends are modeled as the rectangular waveguides with perfect electric conducting top and bottom walls and perfect magnetic conducting side walls. Analytical closed-form expressions for transmission and reflection coefficients are developed using the residue calculus. To verify the proposed method, numerical computations are performed for comparison with 3D full-wave simulations and measurements. A quarter-wavelength transmission line scheme is also proposed to improve the signal integrity of double bend discontinuity.

We present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work.

With the big success of 802.11 wireless networks, there have been many proposals addressing end-to-end QoS guarantees in 802.11 WLAN. However, we have found that current end-to-end QoS architectures lack of one or more important properties such as cross-layer interaction, end-to-end integration, reconfigurability and modularity. In this work, we present an end-to-end reference QoS architecture for 802.11 WLAN that encapsulates in an unifying fashion software-based QoS components (mechanisms, algorithms, services), proposed in the literature. To show the usefulness and correctness of the reference architecture, we present three case studies of end-to-end QoS architectures addressing different QoS requirements such as bandwidth and delay with different approaches such as differentiated services and integrated services. We will give an architectural comparison and performance evaluation of these architectures. We believe the reference QoS architectures can help QoS designers to understand the importance and the complexity of various QoS components during the design phase and thus choose these QoS components appropriately.

Adaptable workflow participant assignment (WPA) is crucial to the efficiency and quality of workflow execution. This paper proposes an ontology-based approach to adaptable WPA (OWPA). OWPA introduces domain ontology to organize the enterprise data and uses a well-defined OWPA rule to express an authorization constraint. OWPA can represent more complex authorization constraints by flexibly using the enterprise data, the workflow data, the user-input data, and the built-in functions. By a high-usability interactive interface, OWPA allows users to define and modify the OWPA rules easily without any programming work. Moreover, OWPA is bound to the workflow modeling tool and the workflow monitor respectively to adapt to dynamic workflow modification in workflow definitions and workflow instances. OWPA has been applied in three enterprises in China.

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100 Mbps. A pair of transceivers consumes 1.35 mA from 3.3 V, at 130 Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30 dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50 dB.

To detect neural spike signals, low-power neural signal recording frontend circuits must amplify neural signals with below 100 µV amplitude and a few hundred Hz frequency while suppressing a large DC offset voltage, 1/f noise of MOSFETs, and induced noise of AC power supply. To overcome the problem of unwanted noise at such a low signal level, a low-noise neural signal detection amplifier with low-frequency noise suppression scheme was developed utilizing a new autozeroing technique. A test chip was designed and fabricated with a mixed signal 0.18-µm CMOS technology. The voltage gain of 39 dB at the bandwidth of the neural signal and the gain reduction of 20 dB at AC supply noise of 60 Hz were obtained. The input equivalent noise and power dissipation were 90 nV/root-Hz and 90 µW at a supply voltage of 1.5 V, respectively.

The design of microstrip bandpass filters using stepped-impedance resonators (SIRs) is examined. The passband center frequency for the WCDMA-FDD (uplink band) Japanese cellular system is 1950 MHz with a 60-MHz bandwidth. The SIR physical characteristic can be designed using a SIR characteristic chart based on second harmonic suppression. In our filter design, passband design charts were obtained through the design procedure. Tchebycheff and maximally flat bandpass filters of any bandwidth and any number of steps can be designed using these passband design charts. In addition, sharp skirt characteristics in the passband can be realized by having two transmission zeros at both adjacent frequency bands by using open-ended quarter-wavelength stubs at input and output ports. A new even-mode harmonics suppression technique is proposed to enable a wide rejection band having a high suppression level. The unloaded quality factor of the resonator used in the proposed filters is greater than 240.

This paper discusses recent trends in the area of low-power, high-performance A/D conversion. We examine survey data collected over the past twelve years to show that the conversion energy of ADCs has halved every two years, while the speed-resolution product has doubled approximately only every four years. A closer inspection on the impact of technology scaling, and developments in ADC design are then presented to explain the observed trends. Finally, we review opportunities in digitally assisted design for the most popular converter architectures.

Cancelable approaches for biometric person authentication have been studied to protect enrolled biometric data, and several algorithms have been proposed. One drawback of cancelable approaches is that the performance is inferior to that of non-cancelable approaches. In this paper, we propose a scheme to improve the performance of a cancelable approach for online signature verification. Our scheme generates two cancelable dataset from one raw dataset and uses them for verification. Preliminary experiments were performed using a distance-based online signature verification algorithm. The experimental results show that our proposed scheme is promising.

An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.