Two essential technologies for a 3D Solid State Drive (3D-SSD) with a boost converter are presented in this paper. The first topic is the spiral inductor design which determines the performance of the boost converter, and the second is the effect of TSV's on the boost converter. These techniques are very important in achieving a 3D-SSD with a boost converter. In the design of the inductor, the on-board inductor from 250 nH to 320 nH is the best design feature that meets all requirements, including high output voltage above 20 V, fast rise time, low energy consumption, and area smaller than 25 mm2. The use of a boost converter with the proposed inductor leads to a reduction of the energy consumption during the write operation of the proposed 1.8-V 3D-SSD by 68% compared with the conventional 3.3-V 3D-SSD with the charge pump. The feasibility of 3D-SSD's with Through Silicon Vias (TSV's) connections is also discussed. In order to maintain the advantages of the boost converter over the charge pump, the reduction of the parasitic resistance of TSV's is very important.

This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 33 mm2 in a 180-nm CMOS process, including 1.38 M transistors. It dissipates 58.0 µW under a network environment.

Performance of band-limited baseband synchronous CDMA using orthogonal Independent Component Analysis (ICA) spreading sequences is investigated. The orthogonal ICA sequences have an orthogonality condition in a synchronous CDMA like the Walsh-Hadamard sequences. Furthermore, these have useful correlation properties like the Gold sequences. These sequences are obtained easily by using the ICA which is one of the brain-style signal processing algorithms. In this study, the ICA is used not as a separator for received signal but as a generator of spreading sequences. The performance of the band-limited synchronous CDMA using the orthogonal ICA sequences is compared with the one using the Walsh-Hadamard sequences. For limiting bandwidth, a Root Raised Cosine filter (RRC) is used. We investigate means and variances of correlation outputs after passing the RRC filter and the Bit Error Rates (BERs) of the system in additive white Gaussian noise channel by numerical simulations. It is found that the BER in the band-limited system using the orthogonal ICA sequences is much lower than the one using the Walsh-Hadamard sequences statistically.

A time-slicing ring oscillator (TSRO) which captures time-dependent delay degradation due to periodic transient voltage drop on a power supply network is proposed. An impact of the supply voltage fluctuations, including voltage drop and overshoot, on logic circuit delay is evaluated as a change of oscillation frequency. The TSRO is designed using standard logic cells so that it can be placed almost anywhere in a digital circuit wherein supply voltage fluctuation is concerned. We also propose a new procedure for reconstructing supply voltage waveform. The procedure enables us to accurately monitor time-dependent, effective supply voltages. The -1 dB bandwidth of the TSRO is simulated to be 15.7 GHz, and measured time resolution is 131 ps. Measurement results of a test chip using 90-nm standard CMOS process successfully proved the feasibility of both delay degradation and effective supply voltage fluctuation measurements. Measurement of spatial voltage drop fluctuation is achieved.

Attacks using hill-climbing methods have been reported as a vulnerability of biometric authentication systems. In this paper, we propose a robust online signature verification algorithm against such attacks. Specifically, the attack considered in this paper is a hill-climbing forged data attack. Artificial forgeries are generated offline by using the hill-climbing method, and the forgeries are input to a target system to be attacked. In this paper, we analyze the menace of hill-climbing forged data attacks using six types of hill-climbing forged data and propose a robust algorithm by incorporating the hill-climbing method into an online signature verification algorithm. Experiments to evaluate the proposed system were performed using a public online signature database. The proposed algorithm showed improved performance against this kind of attack.

This paper presents generating stable and sparse reluctance/inductance matrix from the inductance matrix which is extracted under insufficient discretization. To generate the sparse reluctance matrix with guaranteed stability, the original matrix has to be (strictly) diagonally dominant M matrix. Hence, the repeated inductance extractions with a smaller grid size are necessary in order to obtain the well-defined matrix. Alternatively, this paper provides some ideas for generating the sparse reluctance matrix, even if the extracted reluctance matrix is not diagonally dominant M matrix. These ease the extraction tasks greatly. Furthermore, the sparse inductance matrix is also generated by using double inverse methods. Since reluctance components are not still supported in SPICE-like simulators, generating the sparse inductance matrix is more useful than the sparse reluctance one.

Limitations are found in the recent Internet because a lot of functions and protocols are patched to the original suite of layered protocols without considering global optimization. This reveals that end-to-end argument in the original Internet was neither sufficient for the current societal network and nor for a sustainable network of the future. In this position paper, we present design guidelines for a future network, which we call the New Generation Network, which provides the inclusion of diverse human requirements, reliable connection between the real-world and virtual network space, and promotion of social potentiality for human emergence. The guidelines consist of the crystal synthesis, the reality connection, and the sustainable & evolutional guidelines.

In this letter, we propose a distributed channel assignment where each basestation selects a set of channels shared by multiple users through time domain scheduling for best effort services. The proposed scheme distributedly assigns the channels considering a cochannel interference from neighboring basestations and its own traffic load condition. The computer simulation demonstrates that the proposed scheme appropriately assigns the channels to the basestations taking into account these requirements.

Recently, the marginalized particle filter (MPF) has been applied to blind symbol detection problems over selective fading channels. The MPF can ease the computational burden of the standard particle filter (PF) while offering better estimates compared with the standard PF. In this paper, we investigate the application of the blind MPF detector to more realistic situations where the systems suffer from analog imperfections which are non-linear signal distortion due to the inaccurate analog circuits in wireless devices. By reformulating the system model using the widely linear representation and employing the auxiliary variable resampling (AVR) technique for estimation of the imperfections, the blind MPF detector is successfully modified to cope with the analog imperfections. The effectiveness of the proposed MPF detector is demonstrated via computer simulations.

The precise noise modeling of complementary metal oxide semiconductor image sensor (CMOS image sensor: CIS) is a significant key in understanding the noise source mechanisms, optimizing sensor design, designing noise reduction circuit, and enhancing image quality. Therefore, this paper presents an accurate random telegraph signal (RTS) noise analysis model and a novel quantitative evaluation method in motion picture for the visual sensory evaluation of CIS. In this paper, two main works will be introduced. One is that the exposure process of a video camera is simulated, in which a Gaussian noise and an RTS noise in pinned-photodiode CMOS pixels are modeled in time domain and spatial domain; the other is that a new video quality evaluation method for RTS noise is proposed. Simulation results obtained reveal that the proposed noise modeling for CIS can approximate its physical process and the proposed video quality evaluation method for RTS noise performs effectively as compared to other evaluation methods. Based on the experimental results, conclusions on how the spatial distribution of an RTS noise affects the quality of motion picture are carried out.

Capacitance charging modeling efficiently captures power supply currents in dynamic operations of a CMOS digital circuit and accurately expresses their interaction with on- and off-chip impedance networks. Derivation of such models is generally defined for combinational and sequential logic functions. Simulated substrate and power noises due to sequential logic operation show clear dependency on the size of circuits as well as the internal activity of logic gates. Furthermore, it is experimentally found that the inclusion of impedance networks of a silicon substrate, a package, and an evaluation board, is substantially effective to improve the accuracy of noise analysis. Quantitative correlation among simulation with on-chip noise measurements is demonstrated in a 90-nm 1.2-V CMOS technology.

This paper presents a selective scan slice grouping technique for test data compression. In conventional selective encoding methods, the existence of a conflict bit contributes to large encoding data. However, many conflict bits are efficiently removed using the scan slice grouping technique, which leads to a dramatic improvement of encoding efficiency. Experiments performed with large ITC'99 benchmark circuits presents the effectiveness of the proposed technique and the test data volume is reduced up to 92% compared to random-filled test patterns.

In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitance. The methodology was validated by designing several MCML circuits in an IBM 130 nm CMOS process.

This paper proposes a new hybrid scheme based on a given set of channels for preventing channel interference and collision in mobile networks. The proposed scheme is designed for improving system performance, focusing on enhancement of performance related to path breakage and channel interference. The objective of this scheme is to improve the performance of inter-node communication. Simulation results from this paper show that the new hybrid scheme can reduce a more control message overhead than a conventional random scheme.

An analog circuit testing scheme is presented. The testing technique is a sinusoidal fault signature characterization, involving the measurement of DC offset, amplitude, frequency and phase shift, and the realization of two crossing level voltages. The testing system is an extension of the IEEE 1149.4 standard through the modification of an analog boundary module, affording functionalities for both on-chip testing capability, and accessibility to internal components for off-chip testing. A demonstrating circuit-under-test, a 4th-order Gm-C low-pass filter, and the proposed analog testing scheme are implemented in a physical level using 0.18-µm CMOS technology, and simulated using Hspice. Both catastrophic and parametric faults are potentially detectable at the minimum parameter variation of 0.5%. The fault coverage associated with CMOS transconductance operational amplifiers and capacitors are at 94.16% and 100%, respectively. This work offers the enhancement of standardizing test approach, which reduces the complexity of testing circuit and provides non-intrusive analog circuit testing.

Ultrasonic imaging is useful in seabed or lakebed observations. We can roughly estimate the sea depth by hearing the echo generated by the boundary of water and rocks or sand. However, the estimation quality is usually not sufficient to draw seabed landscape since the echo signal includes serious distortion caused by autointerference. This paper proposes a novel method to visualize the shape of distant boundaries, such as the seawater-rock/sand boundary, based on the complex-valued Markov random field (CMRF) model. Our method realizes adaptive compensation of distortion without changing the global features in the measurement data, and obtains higher-quality landscape with less computational cost than conventional methods.

Evolvable hardware (EHW) is a new research field about the use of Evolutionary Algorithms (EAs) to construct electronic systems. EHW refers in a narrow sense to use evolutionary mechanisms as the algorithmic drivers for system design, while in a general sense to the capability of the hardware system to develop and to improve itself. Genetic Algorithm (GA) is one of typical EAs. We propose optimal circuit design by using GA with parameterized uniform crossover (GApuc) and with fitness function composed of circuit complexity, power, and signal delay. Parameterized uniform crossover is much more likely to distribute its disruptive trials in an unbiased manner over larger portions of the space, then it has more exploratory power than one and two-point crossover, so we have more chances of finding better solutions. Its effectiveness is shown by experiments. From the results, we can see that the best elite fitness, the average value of fitness of the correct circuits and the number of the correct circuits of GApuc are better than that of GA with one-point crossover or two-point crossover. The best case of optimal circuits generated by GApuc is 10.18% and 6.08% better in evaluating value than that by GA with one-point crossover and two-point crossover, respectively.

The Wireless Sensor Network (WSN) uses autonomous sensor nodes to monitor a field. These sensor nodes sometimes act as relay nodes for each other. In this paper, the performance of the WSN using fixed relay nodes and Multiple-Input Multiple-Output (MIMO) technology necessary for future wireless communication is evaluated in terms of the channel capacity of the MIMO system and the number of sensor nodes served by the system. Accordingly, we propose an optimum topology for the WSN backbone named Connected Relay Node Double Cover (CRNDC), which can recover from a single fault, the algorithms (exhaustive search and other two approximation methods) to find the optimum distance to place the relay nodes from sink node, and the height of the sink and relay nodes to be placed by using the pathloss model. The performances of different MIMO-WSN configurations over conventional WSN are evaluated, and the direct relationship between relay position and minimum required channel capacity are discovered.

Lots of revocable group signature schemes have been proposed so far. In one type of revocable schemes, signing and/or verifying algorithms have O(N) or O(R) complexity, where N is the group size and R is the number of revoked members. On the other hand, in Camenisch-Lysyanskaya scheme and the followers, signing and verifying algorithms have O(1) complexity. However, before signing, the updates of the secret key are required. The complexity is O(R) in the worst case. In this paper, we propose a revocable scheme with signing and verifying of O(1) complexity, where any update of secret key is not required. The compensation is the long public key of O(N). In addition, we extend it to the scheme with O()-size public key, where signing and verifying have constant extra costs.

This letter deals with the time-domain estimation of time-varying channels in orthogonal frequency-division multiplexing (OFDM) systems. The general complex exponential basis expansion model (GCE-BEM) is used to capture the time variation of the channel within an OFDM block. The design criterion of optimal training for OFDM systems in time-varying channels is derived. This optimal training enables the complete elimination of the interference from data symbols and minimizes the noise effect on channel estimation. The design criterion can be used for both pilot symbol aided modulation (PASM) and superimposed training OFDM systems over time-varying channels.