The Wireless Sensor Network (WSN) uses autonomous sensor nodes to monitor a field. These sensor nodes sometimes act as relay nodes for each other. In this paper, the performance of the WSN using fixed relay nodes and Multiple-Input Multiple-Output (MIMO) technology necessary for future wireless communication is evaluated in terms of the channel capacity of the MIMO system and the number of sensor nodes served by the system. Accordingly, we propose an optimum topology for the WSN backbone named Connected Relay Node Double Cover (CRNDC), which can recover from a single fault, the algorithms (exhaustive search and other two approximation methods) to find the optimum distance to place the relay nodes from sink node, and the height of the sink and relay nodes to be placed by using the pathloss model. The performances of different MIMO-WSN configurations over conventional WSN are evaluated, and the direct relationship between relay position and minimum required channel capacity are discovered.

In this paper, we design and analyze some new and practical (selectively) convertible undeniable signature (SCUS) schemes in both random oracle and standard model, which enjoy several merits over existing schemes in the literature. In particular, we design the first practical RSA-based SCUS schemes secure in the standard model. On the path, we also introduce two moduli RSA assumptions, including the strong twin RSA assumption, which is the RSA symmetry of the strong twin Diffie-Hellman assumption (Eurocrypt'08).

Femto cell systems have been the one of the key technologies for ubiquitous networks, and some of them are already serviced by manufacturers. Femto base stations are deployed randomly and without pre-planning, so the femto system has a wider variation in topology than cellular networks. Therefore, a specialized resource assignment algorithm is essential for efficient performance of the femto cell. In this paper, we propose a realtime channel assignment algorithm for adapting to the varying environments, including new cell deployment or power switch off. Our algorithm is a form of a sequential graph coloring problem which outperforms other fixed allocation algorithms. Simulation results show realtime assignment has better performance than the fixed allocation when the wireless environment changes faster than the tracking operation time.

We propose a method of assigning polarity to causal information extracted from Japanese financial articles concerning business performance of companies. Our method assigns polarity (positive or negative) to causal information in accordance with business performance, e.g. "zidousya no uriage ga koutyou: (Sales of cars are good)" (The polarity positive is assigned in this example). We may use causal expressions assigned polarity by our method, e.g., to analyze content of articles concerning business performance circumstantially. First, our method classifies articles concerning business performance into positive articles and negative articles. Using them, our method assigns polarity (positive or negative) to causal information extracted from the set of articles concerning business performance. Although our method needs training dataset for classifying articles concerning business performance into positive and negative ones, our method does not need a training dataset for assigning polarity to causal information. Hence, even if causal information not appearing in the training dataset for classifying articles concerning business performance into positive and negative ones exist, our method is able to assign it polarity by using statistical information of this classified sets of articles. We evaluated our method and confirmed that it attained 74.4% precision and 50.4% recall of assigning polarity positive, and 76.8% precision and 61.5% recall of assigning polarity negative, respectively.

In this paper, a novel decentralised dynamic sub-carrier assignment (DSA) algorithm for orthogonal frequency division multiple access (OFDMA)-based adhoc and cellular networks operating in time division duplexing (TDD) mode is proposed to solve the hidden and exposed node problem in media access control (MAC). This method reduces the co-channel interference (CCI), and thus increases the overall throughput of the network. Reduced CCI and increased throughput can be achieved, if time and frequency selectivity of the multi-path fading channel and the channel reciprocity offered by the TDD are fully exploited. The time and frequency selectivity of the channel are usually the main problem in mobile communication. However, in the context of channel assignment for OFDMA-based networks in TDD mode, the time and frequency selectivity of the channel are the key to reduce the interference. In the proposed channel assignment mechanism, several clusters of sub-carriers are assigned for data transmission between a transmitter and a receiver only if the corresponding channels of those sub-carriers linking this transmitter to potential victim receivers are deeply faded. In addition, the proposed algorithm works in a fully decentralised fashion and, therefore, it is able to effectively support ad hoc and multihop communication as well as network self-organisation. Numerical results show that the throughput obtained by the proposed approach for a given quality of service is higher than those of the conventional methods in any precondition of adhoc geographic scenario.

In this paper, we use frequency-domain equalization (FDE) to create coherent optical single-carrier (CO-SC) transmission systems that are very tolerant of chromatic dispersion (CD) and polarization mode dispersion (PMD). The efficient transmission of a 25-Gb/s NRZ-QPSK signal by using the proposed FDE is demonstrated under severe CD and PMD conditions. We also discuss the principle of FDE and some techniques suitable for implementing CO-SC-FDE. The results show that a CO-SC-FDE system is very tolerant of CD and PMD and can achieve high transmission rates over single mode fiber without optical dispersion compensation.

When cognitive radio (CR) systems dynamically use the frequency band, a control signal is necessary to indicate which carrier frequencies are currently available in the network. In order to keep efficient spectrum utilization, this control signal also should be transmitted based on the channel conditions. If transmitters dynamically select carrier frequencies, receivers have to receive control signals without knowledge of their carrier frequencies. To enable such transmission and reception, this paper proposes a novel scheme called DCPT (Differential Code Parallel Transmission). With DCPT, receivers can receive low-rate information with no knowledge of the carrier frequencies. The transmitter transmits two signals whose carrier frequencies are spaced by a predefined value. The absolute values of the carrier frequencies can be varied. When the receiver acquires the DCPT signal, it multiplies the signal by a frequency-shifted version of the signal; this yields a DC component that represents the data signal which is then demodulated. The performance was evaluated by means of numerical analysis and computer simulation. We confirmed that DCPT operates successfully even under severe interference if its parameters are appropriately configured.

Multitude parameters in the design process of a reconfigurable instruction-set processor (RISP) may lead to a large design space and remarkable complexity. Quantitative design approach uses the data collected from applications to satisfy design constraints and optimize the design goals while considering the applications' characteristics; however it highly depends on designer observations and analyses. Exploring design space can be considered as an effective technique to find a proper balance among various design parameters. Indeed, this approach would be computationally expensive when the performance evaluation of the design points is accomplished based on the synthesis-and-simulation technique. A combined analytical and simulation-based model (CAnSO**) is proposed and validated for performance evaluation of a typical RISP. The proposed model consists of an analytical core that incorporates statistics collected from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. CAnSO has clear speed advantages and therefore it can be used for easing a cumbersome design space exploration of a reconfigurable RISP processor and quick performance evaluation of slightly modified architectures.

Many signal processing systems, particularly in the multimedia and telecommunication domains, are synthesized to execute data-intensive applications: their cost related aspects -- namely power consumption and chip area -- are heavily influenced, if not dominated, by the data access and storage aspects. This paper presents an energy-aware memory allocation methodology. Starting from the high-level behavioral specification of a given application, this framework performs the assignment of the multidimensional signals to the memory layers -- the on-chip scratch-pad memory and the off-chip main memory -- the goal being the reduction of the dynamic energy consumption in the memory subsystem. Based on the assignment results, the framework subsequently performs the mapping of signals into both memory layers such that the overall amount of data storage be reduced. This software system yields a complete allocation solution: the exact storage amount on each memory layer, the mapping functions that determine the exact locations for any array element (scalar signal) in the specification, and an estimation of the dynamic energy consumption in the memory subsystem.

The researches on predicting and removing of lithographic hot-spots have been prevalent in recent semiconductor industries, and known to be one of the most difficult challenges to achieve high quality detection coverage. To provide physical design implementation with designer's favors on fixing hot-spots, in this paper, we present a noble and accurate hot-spot detection method, so-called "leveling and scoring" algorithm based on weighted combination of image quality parameters (i.e., normalized image log-slope (NILS), mask error enhancement factor (MEEF), and depth of focus (DOF)) from lithography simulation. In our algorithm, firstly, hot-spot scoring function considering severity level is calibrated with process window qualification, and then least-square regression method is used to calibrate weighting coefficients for each image quality parameter. In this way, after we obtain the scoring function with wafer results, our method can be applied to future designs of using the same process. Using this calibrated scoring function, we can successfully generate fixing guidance and rule to detect hot-spot area by locating edge bias value which leads to a hot-spot-free score level. Finally, we integrate the hot-spot fixing guidance information into layout editor to facilitate the user-favorable design environment. Applying our method to memory devices of 60 nm node and below, we could successfully attain sufficient process window margin to yield high mass production.

In this paper, we propose a novel method for gathering sensing information by using an orthogonal narrowband signal for cooperative sensing in cognitive radio. It is desirable to improve the spectrum sensing performance by countering the locality effect of a wireless channel; cooperative sensing by using multiple inputs of sensing information from the surrounding sensing nodes has attracted attention. Cooperative sensing requires that sensing information be gathered at the master node for determining the existence of a primary signal. If the used information gathering method leads to redundancies, the total capacity of the secondary networks is not improved. In this paper, we propose a novel method for gathering sensing information that maps the sensing information to the orthogonal narrowband signal to achieve simultaneous sensing information gathering at the master node. In this method, the sensing information is mapped to an orthogonal subcarrier signal of an orthogonal frequency division multiplexing (OFDM) structure to reduce the frequency resource required for sensing information gathering. The orthogonal signals are transmitted simultaneously from multiple sensing nodes. This paper evaluates the performance of the proposed information gathering method and confirms its effectiveness.

This paper presents a novel method using multi-objective optimization algorithm to automatically find the best solution from a topology library of analog circuits. Firstly this method abstracts the Pareto-front of each topology in the library by SPICE simulation. Then, the Pareto-front of the topology library is abstracted from the individual Pareto-fronts of topologies in the library followed by the theorem we proved. The best solution which is defined as the nearest point to specification on the Pareto-front of the topology library is then calculated by the equations derived from collinearity theorem. After the local searching using Nelder-Mead method maps the calculated best solution backs to design variable space, the non-dominated best solution is obtained. Comparing to the traditional optimization methods using single-objective optimization algorithms, this work can efficiently find the best non-dominated solution from multiple topologies for different specifications without additional time-consuming optimizing iterations. The experiments demonstrate that this method is feasible and practical in actual analog designs especially for uncertain or variant multi-dimensional specifications.

There is a trend towards flexible radios which are able to cope with a range of wireless communication standards. For the integrated processing of widely different signals -- including single-carrier, multi-carrier, and spread-spectrum signals -- monolithic baseband receivers need universal formats for the signal representation and channel description. We consider a reconfigurable receiver architecture building on concepts from time-frequency (TF) signal analysis. The core elements are TF signal representations in form of a Gabor expansion along with a compatible parameterization of time-variant channels. While applicable to arbitrary signal types, the TF channel parameterization offers similar advantages as the frequency domain channel description employed by orthogonal frequency-division multiplexing receivers. The freedom in the choice of the underlying analysis window function and the scalability in time and frequency facilitate the handling of diverse signal types as well as the adaptation to radio channels with different delay and Doppler spreads. Optimized window shapes limit the inherent model error, as demonstrated using the example of direct-sequence spread-spectrum signaling.

Recently, two-level cache, L1 cache and L2 cache, is commonly used in a processor. Particularly in an embedded system whereby a single application or a class of applications is repeatedly executed on a processor, its cache configuration can be customized such that an optimal one is achieved. An optimal two-level cache configuration can be obtained which minimizes overall memory access time or memory energy consumption by varying the three cache parameters: the number of sets, a line size, and an associativity, for L1 cache and L2 cache. In this paper, we first extend the L1 cache simulation algorithm so that we can explore two-level cache configuration. Second, we propose two-level cache design space exploration algorithms: CRCB-T1 and CRCB-T2, each of which is based on applying Cache Inclusion Property to two-level cache configuration. Each of the proposed algorithms realizes exact cache simulation but decreases the number of cache hit/miss judgments by a factor of several thousands. Experimental results show that, by using our approach, the number of cache hit/miss judgments required to optimize a cache configurations is reduced to 1/50-1/5500 compared to the exhaustive approach. As a result, our proposed approach totally runs an average of 1398.25 times faster compared to the exhaustive approach. Our proposed cache simulation approach achieves the world fastest two-level cache design space exploration.

Low Power Design has become a significant requirement when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for both dynamic and static power reduction while maintaining performance. Level shifters may cause area and Interconnect Length Overhead (ILO), and should be considered at both floorplanning and post-floorplanning stages. In this paper, we propose a two phases algorithm framework, called VLSAF, to solve voltage and level shifter assignment problem. At floorplanning phase, we use a convex cost network flow algorithm to assign voltage and a minimum cost flow algorithm to handle level-shifter assignment. At post-floorplanning phase, a heuristic method is adopted to redistribute white spaces and calculate the positions and shapes of level shifters. The experimental results show VLSAF is effective.

In recent VLSI systems, signal propagation delays are requested to achieve the specifications with very high accuracy. In order to meet the specifications, the routing of a net often needs to be detoured in order to increase the routing delay. A routing method should utilize a routing area with obstacles as much as possible in order to realize the specifications of nets simultaneously. In this paper, a fast longer path algorithm that generates a path of a net in routing grid so that the length is increased as much as possible is proposed. In the proposed algorithm, an upper bound for the length in which the structure of a routing area is taken into account is used. Experiments show that our algorithm utilizes a routing area with obstacles efficiently.

In this paper, we propose a routing method for 2-layer ball grid array packages that generates a routing pattern satisfying a design rule. In our proposed method, the routing structure on each layer is restricted while keeping most of feasible patterns to efficiently obtain a feasible routing pattern. A routing pattern that satisfies the design rule is formulated as a mixed integer linear programming. In experiments with seven data, we obtain a routing pattern such that satisfies the design rule within a practical time by using a mixed integer linear programming solver.

3D graphics application is widely used in consumer electronics which is an inevitable tendency in the future. In general, the higher abstraction level is used to model a complex system like 3D graphics SoC. However, the concerned issue is that how to use efficient methods to traverse design space hierarchically, reduce simulation time, and refine the performance fast. This paper demonstrates a system-level design space exploration model for a tile-based 3D graphics SoC refinement. This model uses UML tools which can assist designers to traverse the whole system and reduces simulation time dramatically by adopting SystemC. As a result, the system performance is improved 198% at geometry function and 69% at rendering function, respectively.

Partial forwarding is a design method to place forwarding paths on a part of processor pipeline. Hardware cost of processor can be reduced without performance loss by partial forwarding. However, compiler with the instruction scheduler which considers partial forwarding structure of the target processor is required since conventional scheduling algorithm cannot make the most of partial forwarding structure. In this paper, we propose a heuristic instruction scheduling method for processors with partial forwarding structure. The proposed algorithm uses available distance to schedule instructions which are suitable for the target partial forwarding processor. Experimental results show that the proposed method generates near-optimal solutions in practical time and some of the optimized codes for partial forwarding processor run in the shortest time among the target processors. It also shows that the proposed method is superior to hazard detection unit.

This paper presents a prototype group modem for a hyper-multipoint data gathering satellite communication system. It can handle arbitrarily and dynamically assigned FDMA signals by employing a novel FFT-type block demultiplexer/multiplexer. We clarify its configuration and operational principle. Experiments show that the developed modem offers excellent performance.