This paper reviews the advantages of the silicon three-dimensional MMIC technology such as low loss transmission lines, high integration level, and high Q-factor on-chip inductors. Coupled to the masterslice concept, this technology also offers simple design procedure, short turn-around-time, low cost, and potential integration with LSI circuits. A K-band amplifier and an up-converter demonstrate the high frequency operation and low-power consumption benefits of the Si 3-D MMIC technology. A C-band Si-bipolar single-chip transceiver is proposed to illustrate the high integration level offered by the masterslice concept. Finally, the recent advances we achieved toward high Q-factor on-chip inductors provide the design of the S-band low noise amplifier presented in this paper.

A 32-bit motor-drive-specific microcontroller chip was newly designed, implemented using a 0.8 µm double-metal CMOS process, and its feasibility was successfully tested by applying the fabricated microcontroller chip to a real AC induction motor drive system. The microcontroller chip includes a single-precision floating-point unit, peripheral devices for motor drive, and a memory controller as well as the SPARC V7 CPU. The pipeline scheme and the two-step multiplication method were used in the multiplier of floating-point unit for the best area and speed trade-off, using the standard cell library available for the design. The chip size is 12.7 12.8 mm2, the number of transistors is around 562,000, and the power consumption is 1.69 W at the supply voltage of 5 V and the clock frequency of 30 MHz. Both a standard cell library and a full-custom layout were used in the implementation.

We have demonstrated the single-chip RF front-end GaAs MMIC for the Japanese Personal Handy-phone System. It has a high efficiency HPA, a T/R switch, a LNA and a low-distortion down converter mixer. The IC employs a negative voltage generator for use of single voltage DC power supply. The HPA provides an output power of 21.5 dBm, with an ACPR of 55 dBc and an efficiency of 35%. The LNA has a noise figure of 1.6 dB and a gain of 14 dB with current of 2.3 mA. The newly developed active cascode FET mixer has a high IIP3 of 1 dBm with a high conversion gain of 10 dB and low consumption current of 2.3 mA. The IC is characterized by high performance for RF front-end of PHS handheld terminals. The IC is available in a 7.0 mm6.4 mm1.1 mm plastic package.

A single-chip GaAs Transmit/Receive (T/R)-MMIC front-end has been developed which is applicable to 1. 9-GHz personal communication terminals such as digital cordless phones. This chip is fabricated using a planar self-aligned gate FET useful for low-cost and high-volume production. The chip integrates RF front-end analog circuits a power amplifier, a T/R-switch, and a low-noise amplifier. Additionally integrated are a newly developed voltage-doubler negative-voltage generator (VDNVG) and a control logic circuit to control transmit and receive functions, enabling both a single-voltage operation and an enhanced power handling capability of the switch, even under a single low-voltage supply condition of 2 V. The power amplifier incorporated onto the chip is capable of delivering a 21 dBm output power at a 39% efficiency, and a 30 dB associated gain with a 2 V single power supply in the transmit mode. The gain and efficiency are higher than those of the previously reported amplifier operating with a 2 V single power supply. The VDNVG produces a step-up voltage of 2. 9 V as well as a negative voltage of -1. 8 V from a 2 V power supply, operating with a charge time of less than 0. 25 µs. The control logic circuit on the chip has a newly designed interface circuit utilizing the step-up voltage and negative voltage, thereby enabling the chip to handle high power outputs over 24 dBm with a low operating voltage of 2 V. In the receive mode, a 1. 7 dB noise figure and a 0. 6 dB insertion loss are achieved with a current dissipation of 3. 6 mA. The developed MMIC, which is the first reported 2 V single-voltage operation T/R-MMIC front-end, is expected to contribute to the size and weight reductions in personal communication terminals.