In this research, we investigated the threshold voltage (VTH) control by partial polarization of metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5 nm-thick nondoped HfO2 gate insulator utilizing Kr-plasma sputtering for Pt gate electrode deposition. The remnant polarization (2Pr) of 7.2 μC/cm2 was realized by Kr-plasma sputtering for Pt gate electrode deposition. The memory window (MW) of 0.58 V was realized by the pulse amplitude and width of -5/5 V, 100 ms. Furthermore, the VTH of MFSFET was controllable by program/erase (P/E) input pulse even with the pulse width below 100 ns which may be caused by the reduction of leakage current with decreasing plasma damage.

In this research, we investigated the metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5nm thick nondoped HfO2 gate insulator by decreasing the sputtering power for Pt gate electrode deposition. The leakage current was effectively reduced to 2.6×10-8A/cm2 at the voltage of -1.5V by the sputtering power of 40W for Pt electrode deposition. Furthermore, the memory window (MW) of 0.53V and retention time over 10 years were realized.

In this research, we investigated the effect of Hf inter layer and chemical oxide on Si(100) substrate on the ferroelectric undoped HfO2 deposition. In case with 1 nm-thick Hf inter layer, equivalent oxide thickness (EOT) was decreased from 6.0 to 4.8 nm for 10 nm-thick HfO2 with decreasing annealing temperature. In case with 0.5 nm-thick chemical oxide, EOT was decreased from 3.9 to 3.6 nm in MFS diodes for 5 nm-thick HfO2. The MFSFET was fabricated with 10 nm-thick HfO2 utilizing Hf inter layer. The subthreshold swing was improved from 240 mV/dec. to 120 mV/dec. and saturation mobility was increased from 70 cm2/(Vs) to 140 cm2/(Vs) by inserting Hf inter layer.

In this paper, the influence of high-temperature sputtering on the nitrogen-doped (N-doped) LaB6 thin film formation utilizing RF sputtering was investigated. The N-doped LaB6/SiO2/p-Si(100) MOS diode and N-doped LaB6/p-Si(100) of Schottky diode were fabricated. A 30 nm thick N-doped LaB6 thin film was deposited from room temperature (RT) to 150°C. It was found that the resistivity was decreased from 1.5 mΩcm to 0.8 mΩcm by increasing deposition temperature from RT to 150°C. The variation of work function was significantly decreased in case that N-doped LaB6 thin film deposited at 150°C. Furthermore, Schottky characteristic was observed by increasing deposition temperature to 150°C. In addition, the crystallinity of N-doped LaB6 thin film was improved by increasing deposition temperature.

In this paper, we have investigated the etching selectivity of HfN encapsulating layer for high quality PtHf-alloy silicide (PtHfSi) formation with low contact resistivity on Si(100). The HfN(10 nm)/PtHf(20 nm)/p-Si(100) stacked layer was in-situ deposited by RF-magnetron sputtering at room temperature. Then, silicidation was carried out at 500°C/20 min in N2/4.9%H2 ambient. Next, the HfN encapsulating layer was etched for 1-10 min by buffered-HF (BHF) followed by the unreacted PtHf metal etching. We have found that the etching duration of the 10-nm-thick HfN encapsulating layer should be shorter than 6 min to maintain the PtHfSi crystallinity. This is probably because the PtHf-alloy silicide was gradually etched by BHF especially for the Hf atoms after the HfN was completely removed. The optimized etching process realized the ultra-low contact resistivity of PtHfSi to p+/n-Si(100) and n+/p-Si(100) such as 9.4×10-9Ωcm2 and 4.8×10-9Ωcm2, respectively, utilizing the dopant segregation process. The control of etching duration of HfN encapsulating layer is important to realize the high quality PtHfSi formation with low contact resistivity.

For the further scaling and lower voltage applications of nonvolatile ferroelectric memory, the effect of Kr/O2 sputtering for SrBi2Ta2O9 (SBT) thin film formation was investigated utilizing a SrBi2Ta2O9 target. The 80-nm-thick SBT films were deposited by radio-frequency (RF) magnetron sputtering on Pt/Ti/SiO2/Si(100). Compared with Ar/O2 sputtering, the ferroelectric properties such as larger remnant polarization (Pr) of 3.2 μC/cm2 were observed with decrease of leakage current in case of Kr/O2 sputtering. X-ray diffraction (XRD) patterns indicated that improvement of the crystallinity with suppressing pyrochlore phases and enhancing ferroelectric phases was realized by Kr/O2 sputtering.

In this study, the effect of atomically flat Si(100) surface on Hf-based Metal-Oxide-Nitride-Oxide-Silicon (MONOS) structure was investigated. After the atomically flat Si(100) surface formation by annealing at 1050/60min in Ar/4%H2 ambient, HfO2(O)/HfN1.0(N)/HfO2(O) structure with thickness of 10/3/2nm, respectively, was in-situ deposited by electron cyclotron resonance (ECR) plasma sputtering. The memory window (MW) of Al/HfO2/HfN1.0/HfO2/p-Si(100) diodes was increased from 1.0V to 2.5V by flattening of Si(100) surface. The program and erase (P/E) voltage/time were set as 10V/5s and -8V/5s, respectively. Furthermore, it was found that the gate current density after the 103P/E cycles was decreased one order of magnitude by flattening of Si(100) surface in Ar/4.0%H2 ambient.

In this paper, we have investigated the PdEr-silicide formation utilizing a developed PdEr-alloy target for sputtering, and evaluated the contact resistivity of PdEr-silicide layer formed on n-Si(100) by dopant segregation process for the first time. Pd2Si and ErSi2 have same hexagonal structure, while the Schottky barrier height for electron (Φbn) is different as 0.75 eV and 0.28 eV, respectively. A 20 nm-thick PdEr-alloy layer was deposited on the n-Si(100) substrates utilizing a developed PdEr-alloy target by the RF magnetron sputtering at room temperature. Then, 10 nm-thick TiN encapsulating layer was in-situ deposited at room temperature. Next, silicidation was carried out by the RTA at 500 for 5 min in N2/4.9%H2 followed by the selective etching. From the J-V characteristics of fabricated Schottky diode, qΦbn was reduced from 0.75 eV of Pd2Si to 0.43 eV of PdEr-silicide. Furthermore, 4.0x10-8Ωcm2 was extracted for the PdEr-silicide to n-Si(100) by the dopant segregation process.

In this paper, we have investigated the characteristics of PdYb-silicide layer formed by the silicidation of Pd/Yb/n-Si(100) stacked structures for the first time. Pd (12-20 nm)/Yb (0-8 nm) stacked layers were deposited on n-Si(100) substrates by the RF magnetron sputtering at room temperature. Then, 10 nm-thick HfN encapsulating layer was deposited at room temperature. Next, silicidation was carried out by the RTA at 500°C/1 min in N2 followed by the selective etching. From the J-V characteristics of fabricated Schottky diode, Schottky barrier height (SBH) for electron was reduced from 0.73 eV of Pd2Si to 0.4 eV of PdYb-silicide in case the Pd/Yb thicknesses were 14/6 nm, respectively.

Crystalline GaN films can be grown even on amorphous substrates with the use of graphene buffer layers by pulsed sputtering deposition (PSD). The graphene buffer layers allowed us to grow highly c-axis-oriented GaN films at low substrate temperatures. Full-color GaN-based LEDs can be fabricated on the GaN/graphene structures and they are operated successfully. This indicates that the present technique is promising for future large-area light-emitting displays on amorphous substrates.

We have investigated PtHf silicide formation utilizing a developed PtHf-alloy target to realize low contact resistivity for the first time. A 20 nm-thick PtHf-alloy thin film was deposited on the n-Si(100) by RF magnetron sputtering at room temperature. Then, silicidation was carried out by rapid thermal annealing (RTA) system at 450-600°C/5 min in N2/4.9%H2 ambient. The PtHf-alloy silcide, PtHfSi, layers were successfully formed, and the Schottky barrier height (SBH) for electron of 0.45 eV was obtained by 450°C silicidation. Furthermore, low contact resistivity was achieved for fabricated PtHSi such as 8.4x10-8 Ωcm2 evaluated by cross-bridge Kelvin resistor (CBKR) method.

To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon (Si) should be realized. In this paper, the influence of Si surface roughness on electrical characteristics of MOSFET with hafnium oxynitride (HfON) gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was investigated for the first time. The surface roughness of Si substrate was reduced by Ar/4.9%H2 annealing utilizing conventional rapid thermal annealing (RTA) system. The obtained root-mean-square (RMS) roughness was 0.07nm (without annealed: 0.18nm). The HfON was formed by 2nm-thick HfN deposition followed by the Ar/O2 plasma oxidation. The electrical properties of HfON gate insulator were improved by reducing Si surface roughness. It was found that the current drivability of fabricated nMOSFETs was remarkably increased by reducing Si surface roughness. Furthermore, the reduction of Si surface roughness also leads to decrease of the 1/f noise.

Deposition of inclined anisotropy film for bit-patterned media was studied using an oblique incidence collimated sputtering. Pt underlayer increased the inclination angle of magnetic layer more than 5° on a Ta seed layer. Further increase of the angle was obtained by annealing Pt/Ru underlayer resulting an inclination angle of 9.4° for a Co-Cr15.5 film on the underlayer. The magnetic properties of the Co-Cr15.5 film with an inclined orientation was estimated comparing measured hysteresis loops with simulated ones, which indicated to have inclined magnetic anisotropy with an anisotropy field of about 4.5kOe and a deflection angle of the anisotropy about the same as that of the crystalline orientation.

To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon should be realized. In this paper, flattening process of Si surface below 1000 utilizing Ar/4.9%H2 annealing and its effect on ultrathin HfON gate insulator formation were investigated. The Si(100) substrates were annealed using conventional rapid thermal annealing (RTA) system in Ar or Ar/4.9%H2 ambient for 1 h. The surface roughness of Ar/4.9%H2-annealed Si was small compared to that of Ar-annealed Si because the surface oxidation was suppressed. The obtained root mean square (RMS) roughness was 0.08 nm (as-cleaned: 0.20 nm) in case of Ar/4.9%H2-annealed at 1000 measured by tapping mode atomic force microscopy (AFM). The HfON surface was also able to be flattened by reduction of Si surface roughness. The electrical properties of HfON gate insulator were improved by the reduction of Si surface roughness. We obtained equivalent oxide thickness (EOT) of 0.79 nm (as-cleaned: 1.04 nm) and leakage current density of 3.510-3 A/cm2 (as-cleaned: 6.110 -1 A/cm2) by reducing the Si surface roughness.

We have studied resistance-switching properties of RF sputtered Si-rich oxides sandwiching with Pt electrodes. By sweeping bias to the top Pt electrode, non-polar type resistance switching was observed after a forming process. In comparison to RF sputtered TiOx case, significant small current levels were obtained in both the high resistance state (HRS) and the low resistance state (LRS). And, even with decreasing SiOx thickness down to 8 nm from 40 nm, the ON/OFF ratio in resistance-switching between HRS and LRS as large as 103 was maintained. From the analysis of current-voltage characteristics for Pt/SiOx on p-type Si(100) and n-type Si(100), it is suggested that the red-ox (REDction and OXidation) reaction induced by electron fluence near the Pt/SiOx interface is of importance for obtaining the resistance-switching behavior.

The metallic waveguide is one of many effective media for millimeter- and submillimeter-waves because of the advantage of its low-loss nature. This paper describes the fabrication method of PTFE-filled waveguide components with the use of the SR (synchrotron radiation) direct etching process of PTFE, sputter deposition of metal, and electroplating. PTFE is known as a difficult material to process with high precision. However, it has been reported that PTFE microstructures can be fabricated by the direct exposure to SR. First, an iris-coupled waveguide BPF with 5-stage Chebyshev response is designed and fabricated for the Q-band. It is demonstrated that the present process is applicable for the fabrication of the practical components inclusive of narrow patterns. Then, a cruciform 3 dB coupler with air-filled posts is designed and fabricated for the Q-band. Directivity and matched state of the coupler can be realized by “holes” in the dielectric material. The measurement results are also shown.

The authors describe a method to produce gold nanoparticle-dispersed liquid crystals by means of sputtering, and discuss how the presence of gold nanoparticles affect the electro-optic response of the host liquid crystal. The method exploits the fact that liquid crystals possess low vapor pressures which allow them to undergo the sputtering process, and the target material is sputtered directly on the liquid crystal in a reduced air pressure environment. The sample attained a red-brownish color after sputtering, but no aggregations were observed in the samples kept in the liquid crystal phase. Polarization optical microscopy of the sample placed in a conventional sandwich cell revealed that the phase transition behaviour is affected by the presence of the nanoparticles and that the onset of the nematic phase is observed in the form of bubble-like domains whereas in the pure sample the nematic phase appears after the passing of a phase transition front. Transmission electron microscopy confirmed the presence of single nano-sized particles that were dispersed without forming aggregates in the material. The electro-optic properties of the nanoparticle-dispersed liquid crystal was investigated by measuring the threshold voltage for a twisted-nematic cell. The threshold voltage was found to depend on the frequency of the applied rectangular voltage, and at frequencies higher than 200 Hz, the threshold became lower than the pure samples.

Al doped zinc oxide (AZO) films were deposited using a radio frequency (rf) magnetron sputtering apparatus with a mesh grid electrode. Improvement of crystalline uniformity was achieved by the use of an appropriate negative grid bias to effectively suppress the bombardment of high-energy charged particles onto the film surface. The uniformity of the film's electronic properties, such as resistivity, carrier concentration and Hall mobility, was also improved using the sputtering method. Hydrogen plasma annealing was investigated to further decrease the resistivity of the ZnO films and the carrier concentration was increased by 1-21020 cm-3 without decrease in the Hall mobility.

Carbon nanofibers (CNFs) were fabricated on graphite plates using "Ar+ ion sputtering method" in large amount at room temperature. The morphology of CNFs was controlled by a simultaneous carbon supply during ion sputtering. CNF-tipped cones were formed on graphite plate surfaces without carbon supply whereas those with a simultaneous carbon supply featured mainly needle-like protrusions of large size. The field electron emission (FE) properties, measured using parallel plate configurations in 10-4 Pa range, showed the threshold fields of 4.4 and 5.2 V/µm with a current density of 1 µA/cm2 for CNF-tipped cones and needle-like protrusion, respectively. Reliability test results indicated that CNF-tipped cones were more stable than needle-like protrusion. The morphological change after reliability test showed a so-called "self-regenerative" process and structure damage for CNF-tipped cones and needle-like protrusions, respectively.

Minimizing the residual impurity gases is a key factor for reducing temporal dark image sticking. Therefore, this paper uses a vacuum-sealing method that minimizes the residual impurity gases by enhancing the base vacuum level, and the resultant change in temporal dark image sticking is then examined in comparison to that with the conventional sealing method using 42-in. ac-PDPs with a high Xe (11%) content. As a result of monitoring the difference in the display luminance, infrared emission, and perceived luminance between the cells with and without temporal dark image sticking, the vacuum-sealing method is demonstrated to reduce temporal dark image sticking by decreasing the residual impurity gases and increasing the oxygen vacancy in the MgO layer. Furthermore, the use of a modified driving waveform along with the vacuum-sealing method is even more effective in reducing temporal dark image sticking.