The constant-Q based wavelet transform is the most effective means of quantitatively characterizing high frequency transient signals. This study develops a novel non constant-Q based multi-resolution transform (NCQM) and provides a precision analysis descriptor for both low and high frequency transients. The properties of this novel NCQM kernel are thoroughly examined and then the striking conceptual resemblance, energy conservation characteristic, and power spectrum close forms are derived. The rapid algorithm of NCQM is also presented and its excellent performance in noisy environments is demonstrated.

Progress in the field of broadband access network and information appliances has led to the advent of a new network field called Home Network. In 1999, HomePNA2.0 using phone line was proposed, and we believe that it is one of the most promising solutions because of its cost-effectiveness. However, due to adaptation of the mature IEEE802.3 CSMA/CD technology used for Ethernet, it is not able to guarantee the QoS. We present the design, implementation and empirical evaluation of a new MAC protocol for the Home Network called HomeMAC. In this paper, the software based HomeMAC is implemented by programming the kernel space of FreeBSD. HomeMAC features a hybrid CSMA/CD-Timed Token protocol which combines the CSMA/CD for non-real-time traffic with timed token protocol for real-time traffic. In addition, by providing flexible bandwidth allocation based on QoS Level Table (QLT), HomeMAC can serve high QoS covering the whole offered load. From the results of evaluation of software implementation, we verify that HomeMAC can provide low delay, low loss, and low jitter to the real-time traffic by reservation of the bandwidth.

As a center of mobile multimedia of the 21st century, it is very much looking forward to explosion of R&D and business of the next generation of mobile communication systems and the ITS (Intelligent Transport Systems) because ITS will enable information-oriented in the field of the road, traffic and vehicles, by using the most advanced technologies of mobile communications and devices, for the various purposes such as decrease of the traffic accident, the reduction of traffic jam, the increase in efficiency of the logistics and the harmony with the earth environment. This invited paper will first briefly introduce evolution of mobile communications and ITS in ministries, industries and academia in Japan. Then core communication technologies for ITS will be overviewed such as spread spectrum CDMA, adaptive antenna array, and software radio or software defined radio. Demands of SoC (System on a Chip) to carry out the core technologies will be addressed.

This letter presents a novel application of the Verilog-A, which is a hardware description language for analog circuits, to the modeling and simulation of high-speed interconnects in time/frequency transform-domain for signal integrity problems. This modeling method with the Verilog-A language would handle the transfer function approximation and admittance matrices, which are expressed by the dominant poles and residues as used in AWE technique. Finally, it is shown that modeling and simulation of the high-speed interconnects with nonlinear terminations can be done easily.

An LSI has been fabricated and measured to demonstrate feasibility of VDD-hopping scheme in an embedded system level by executing MPEG4 CODEC. In the VDD-hopping, supply voltage of a processor is dynamically controlled by a hardware-software cooperative mechanism depending on workload of the processor. When the workload is about a half, the VDD-hopping is shown to reduce power to less than a quarter compared to the conventional fixed-VDD scheme. The power saving is achieved without degrading real-time features of MPEG4 CODEC.

This paper presents an explicit analysis of the output error power in wideband sampling systems with finite aperture time in the presence of sampling jitter. Sampling jitter and finite aperture time affect the ability of wideband sampling systems to capture high-frequency signals with high precision. Sampling jitter skews data acquisition timing points, which causes large errors in high-frequency (large slew rate) signal acquisition. Finite sampling-window aperture works as a low pass filter, and hence it degrades the high-frequency performance of sampling systems. In this paper, we discuss these effects explicitly not only in the case that either sampling jitter or finite aperture time exists but also the case that they exist together, for any aperture window function (whose Fourier transform exists) and sampling jitter of Gaussian distribution. These would be useful for the designer of wideband sampling data acquisition systems to know how much sampling jitter and aperture time are tolerable for a specified SNR. Some experimental measurement results as well as simulation results are provided as validation of the analytical results.

The jitter characteristics of synchronous residual time stamp (SRTS) method used in ATM adaptation layer type 1 (AAL1) are analyzed. In this letter, the root mean square amplitude of filtered SRTS jitter is calculated and the computer simulation has been carried out to show jitter of SRTS method considering also the phase time error of network clocks.

In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache. " The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.

A cascode crystal oscillator is widely used for the stable frequency source of mobile communication equipments. Recently, IC production of the cascode crystal oscillator has become necessary. The cascode crystal oscillator is composed of a colpitts crystal oscillator and a cascode connected base-common buffer amplifier. The base bypass condenser prevents the area size reduction. In this paper, we have proposed the new structures of the cascode crystal oscillator suitable for integrated circuits. The proposed circuits have the advantages on reduction of the area size and start-up time without deteriorating the frequency stability against the load impedance variation and other performances. The simulation and experiment have shown the effectiveness of the proposed circuits.

Sophisticated and robust resource management is an essential issue in future wireless systems which will provide a variety of application services. In this paper, we employ an adaptive-network-based fuzzy inference system (ANFIS) to control the resource allocation for mobile multimedia networks. ANFIS, possessing the advantages of expert knowledge of fuzzy logic system and learning capability of neural networks, can provide a systematic approach to finding appropriate parameters for the Sugeno fuzzy model. The fuzzy resource allocation controller (FRAC) is designed in a two-layer architecture and selects properly the capacity requirement of new call request, the capacity reservation for future handoffs, and the air interface performance as input linguistic variables. Therefore, the statistical multiplexing gain of mobile multimedia networks can be maximized in the FRAC. Simulation results indicate that the proposed FRAC can keep the handoff call blocking rate low without jeopardizing the new call blocking rate. Also, the FRAC can indeed guarantee quality of service (QoS) contracts and achieve higher system performance according to network dynamics, compared with the guard channel scheme and ExpectedMax strategy.

Today, an ultra-high capacity transmission system based on N40 Gb/s channel rate is the most promising approach to achieve multi-terabit/s of capacity over a single fiber. We have demonstrated 5.12 Tbit/s transmission of 128 channels at 40 Gbit/s over 3100 km and 10.24 Tbit/s transmission of 256 channels at 42.6 Gbit/s (using FEC) over 100 km, based on four main technologies: 40 Gbit/s electrical time-division multiplexing (ETDM), vestigial sideband demultiplexing (VSB), advanced amplifier technology including Raman amplification and TeraLightTM fiber. A record spectral efficiency of 1.28 bit/s/Hz is applied to achieve 10.24 Tbit/s transmission within the C- and L-band.

An on-chip, 64-Mb, embedded, DRAM MPEG-2 encoder LSI with a multimedia processor has been developed. To implement this large-scale and high-speed LSI, we have developed the hierarchical skew control of multi-clocks, with timing verification, in which cross-talk noise is considered, and simple measures taken against the IR drop in the power lines through decoupling capacitors. As a result, the target performance of 263 MHz at 1.5 V has been successfully attained and verified, the cross-talk noise has been considered, and, in addition, it has become possible to restrain the IR drop to 166 mV in the 162 MHz operation block.

This paper investigates the accepting powers of one-way alternating and deterministic multi-counter automata operating in realtime. We partially solve the open problem posed in [4], and show that for each k1, there is a language accepted by a realtime one-way deterministic (k+3)-counter automaton, but not accepted by any realtime one-way alternating k-counter automaton.

40 Gbit/s optical transceiver using a novel OTDM MUX module has been developed. OTDM (Optical-Time-Division-Multiplexing) MUX module, the core component of the transmitter, consisted of a optical splitter, two electro-absorption (EA) modulators and a combiner in a sealed small package. As the split optical paths run through the "air" in the module, greatly stable optical phase relation between bit-interleaved pulses could be maintained. With the OTDM MUX module, the selection between conventional Return-to-Zero (conventional-RZ) format and carrier-suppressed RZ (CS-RZ) format is performed by slightly changing the wavelength of laser-diode. In a receiver, 40 Gbit/s optical data train is optically demultiplexed to 10 Gbit/s optical train, before detected by the O/E receiver for 10 Gbit/s RZ format. Back-to-back MUX-DEMUX evaluations of the transceiver exhibited good sensitivities of under -30 dBm measured at 40 Gbit/s optical input to achieve the bit-error-rate (BER) of 10-9. Another unique feature of the transceiver system was a spectrum switch capability. The stable RZ and CS-RZ multiplexing operation was confirmed in the experiment. Once we adjust the 40 Gbit/s optical signal to CS-RZ format, the optical spectrum would maintain its CS spectrum shape for a long time to the benefit of the stable long transmission characteristics. In the recirculating loop experiment employing the OTDM MUX transceiver, the larger power margin was successfully observed with CS-RZ format than with conventional-RZ format, indicating that proper encoding of conventional-RZ and CS-RZ was realized with this prototype transceiver. In the case of CS-RZ format, the error free (BER < 10-9) transmission over 720 km was achieved with the long repeater amplifier span of 120 km.

Media processing has become one of the dominant computing workloads. In this context, SIMD instructions have been introduced in current processors to raise performance, often the main goal of microprocessor designers. Today, however, designers have become concerned with the power consumption, and in some cases low power is the main design goal (laptops). In this paper, we show that SIMD ISA extensions on a superscalar processor can be one solution to reduce power consumption and keeping a high performance level. We reduce the average power consumption by decreasing the number of instructions, the number of cache references, and using dynamic power management to transform the speedup in performance in power consumption reduction.

Improvement of the absorbing boundary conditions for triangle-hexagonal dual cell grids in the time domain method is described in this paper. The magnetic field components, which are evaluated by the electric fields at the circumcenters of the triangle cells, are conformed to Berenger's perfectly matched layer absorbing boundary conditions. The electric field is linearly interpolated by the fields at the vertices. The lower reflection coefficients in the frequency range for the equilateral and non-equilateral triangle cells are demonstrated.

In this paper, we propose an algorithm to calculate the higher moments of the busy period length of a discrete-time M/G/1 type queue with finite buffer. The queueing model has a level-dependent transition probability matrix. Our algorithm is given as a set of recursive formulas which are derived from the relationship among the generating function matrices of the fundamental period. As an example of our algorithm, we provide an approximate analysis of a HOL (Head Of Line) priority control queue.

The reverse link signal power required for multimedia traffic in multipath faded single-code (SC-) and multi-code CDMA (MC-CDMA) systems is investigated. The effect of orthogonality loss among multiple spreading code channels is characterized by introducing the orthogonality factor. The required signal power in both CDMA systems is analyzed with varying system parameters of spreading bandwidth, the orthogonality factor, and the number of spreading codes. Analytical results show that MC-CDMA users transmitting only a single traffic type require significantly more power than SC-CDMA users with only a single traffic type. On the other hand, MC-CDMA users transmitting multimedia traffic require power levels approximately identical to SC-CDMA users with multimedia traffic.

Time stamping is a technique used to prove the existence of certain digital data prior to a specific point in time. With the recent expansion of electronic commerce, it has been widely recognized as an important technique for ensuring the integrity of digital data for a long time period. Recently, various time stamping schemes have been proposed. However, a framework for evaluating their security and cost has not yet been established. Therefore, it has been difficult for users and system designers to select appropriate time stamping schemes. This paper presents a new framework for evaluating the security and cost of time stamping schemes. Our framework classifies time stamping schemes into 108 categories and clarifies their characteristics with regard to security and cost. By applying our framework to a certain scheme, we can easily evaluate its security and cost without discussing details of its specification. In this paper, we explain the basic idea of our framework and show how to use it by applying it to four existing schemes: Digital Notary/SecureSeal, PKITS, TIMESEC and Cuculus.

Fast packet switches for variable-size packets have become an everyday necessity with the rapid growth in the volume of Internet traffic. Such switches can be designed in two different ways, either by segmenting packets into smaller fixed-size cells and designing packet switches for such cells, or by designing generic packet switches for variable-size packets, where packet segmentation and reassembly can be omitted. The second option is investigated in this paper. The synchronous operation mode with time-limited bulk service is selected. The switching fabric is assumed to be internally non-blocking and provided with input queues. A previous maximum switch throughput analysis has been done under the assumption that the length of the time slot is fixed set to its minimum allowed value (Tmin). In this work, a so-called time-slot stretch factor (SF) is introduced. The actual time-slot length is determined by multiplying Tmin with the SF, where SF. Next, a so-called Internet traffic-source model is proposed based on findings from real IP traffic measurements. The performance implications of the proposed time-slot length modification are analyzed by discrete-event computer simulation. The maximum switch throughput is increased by increasing the SF value, e.g. for uniform packet size distribution and SF=10, the maximum switch throughput is increased from 75% to 97%. The influence of the traffic-source characteristics on the maximum switch throughput is decreased when SF value is increased. In order to prevent any possible throughput degradations, it is advisable to use integer SF values. Packet delay analysis has revealed that by increasing the SF value, the mean packet delay is also increased. Nevertheless, it is shown that the number of switch input and output ports is the most important factor to be considered when packet delay is at stake. Service class differentiation inside investigated packet switch is possible and is not affected by the increasing SF value. Such a packet switch is suitable for implementation in wide area networks, due to high transmission speeds and the small number of switch ports.