Recently many researches concerning heart sound analysis are being processed with development of digital signal processing and electronic components. But there are few researches about recognition of heart sound, especially full cardiac cycled heart sound. In this paper, three new recognition methods about full cardiac cycled heart sound were proposed. The first method recognizes the characteristics of heart sound by integrating important peaks and analyzing statistical variables in time domain. The second method builds a database by principal components analysis on training heart sound set in time domain. This database is used to recognize new input of heart sound. The third method builds the same sort of the database not in time domain but in time-frequency domain. We classify the heart sounds into seven classes such as normal (NO) class, pre-systolic murmur (PS) class, early systolic murmur (ES) class, late systolic murmur (LS) class, early diastolic murmur (ED) class, late diastolic murmur (LD) class and continuous murmur (CM) class. As a result, we could verify that the third method is better efficient to recognize the characteristics of heart sound than the others and also than any precedent research. The recognition rates of the third method are 100% for NO, 80% for PS and ES, 67% for LS, 93 for ED, 80% for LD and 30% for CM.

For the purpose of equalisation of rapidly time variant multipath channels, we derive a novel adaptive algorithm, the amplitude banded LMS (ABLMS), which implements a non-linear adaptation based on a coefficient matrix. Then we develop the ABLMS algorithm as the adaptation procedure for a linear transversal equaliser (LTE) and a decision feedback equaliser (DFE) where a parallel adaptation scheme is deployed. Computer simulations demonstrate that with a small increase of computational complexity, the ABLMS based parallel equalisers provide a significant improvement related to the conventional LMS DFE and the LMS LTE in the case of a second order Markov communication channel model.

We have developed a new traffic measuring tool and applied it to the real-time simulation of a network. It monitors IP traffic on an ATM link and continuously transfers the length and timestamp of each IP packet to a post-processing system. The post-processing system receives the data, estimates the cell's arrival epoch at the transmission queue of the ATM link, and simulates the queueing behavior on-line if conditions differ from those of the actual system. The measuring tool and real-time simulation represent a new approach to traffic engineering. A new estimation problem, the arrival sequence estimation, is shown and some algorithms are proposed and evaluated. Also, a new dimensioning algorithm called the queue decay parameter method, which is expected to be robust and applicable to real-time control, is proposed and evaluated.

This paper proposes a media synchronization scheme with causality control for distributed multimedia applications in which the temporal and causal relationships exist among media streams such as computer data, voice, and video. In the scheme, the Δ-causality control is performed for causality, and the Virtual-Time Rendering (VTR) algorithm, which the authors previously proposed, is used for media synchronization. The paper deals with a networked shooting game as an example of such applications and demonstrates the effectiveness of the scheme by experiment.

By combining the technology of all-optical saturable absorbers and the diffractive optics, a scheme of all-optical time division demultiplexing module is investigated. Following authors' proposal, design, test fabrication of the optical platform in the previous paper, this paper focuses on the characterization of switching performance. Using a multiple quantum well saturable absorber of InGaAs/InAlAs composition, and gain switched semiconductor laser pulses of 25 ps pulse width, the switching function was demonstrated experimentally at wavelength of 1.55 µm. The switching on-off ratio was compared among 4 lens configuration, 2 lens configuration (2L) and free space, collinear geometry. No degradation was observed in the case of 2 lens configuration in comparison to collinear illumination. Thus the feasibility of all-optical switch module with power efficiency and high speed is predicted, under the assumption of the progress in sub-micron lithography.

A multimedia content is usually read-only and composed of multimedia objects with their spatial and temporal specifications. These specifications given by its author can enforce the display of objects to be well organized for its context. When multimedia contents are serviced in network environment by an on-demand basis, the temporal relationship among the objects can be used to improve the performance of the service. This paper models the temporal relationship as a scenario that represents the presentation order of the objects in a scenario and proposes several scheduling methods that make it possible to rearrange the transmission order of objects in a scenario. As a result, system resources such as computing power and network bandwidth can be highly utilized. Since the temporal relationship of a scenario is static, it is possible to reduce the scheduling overhead of a server by pre-scheduling currently servicing scenarios. In addition, several simulation results are presented in order to compare and analyze the characteristics of the proposed methods.

Equivalent-time sampling is a well-known technique to capture repetitive signals at finer time intervals than a sampling clock cycle time and it is widely used to implement waveform measurement with high time resolution. There are three techniques for implementing its time base (i.e., sequential sampling, random sampling and coherent sampling), and they have their respective advantages and disadvantages. In this paper we propose a new coherent sampling system which incorporates a pretrigger and time jitter reduction function for a fluctuating input signal which a random sampling system has, while maintaining the waveform recording efficiency of a conventional coherent sampling system. We also report on a technique for measuring a reference trigger time period accurately which is necessary to implement the proposed sampling system, and show its effectiveness through numerical calculations of its data recording time.

The k-vertex-connectivity augmentation problem for a specified set of vertices of a graph with degree-unchangeable vertices, kVCA(G,S,D), is defined as follows: "Given a positive integer k, an undirected graph G=(V,E), a specified set of vertices S V and a set of degree-changeable vertices D V, find a smallest set of edges E such that the vertex-connectivity of S in (V,E E) is at least k and E {(u,v) u,v D}. " The main result of the paper is that checking the existence of a solution and finding a solution to 2VCA(G,S,D) or 3VCA(G,S,D) can be done in O(|V|+|E|) or O(|V|(|V|+|E|)) time, respectively.

FDMA/TDMA non-geostationary earth orbit satellite systems (Non-GEOS) generally require a pre-planned pool of radio resource, i.e., frequency and time slot plan (FTSP), for each gateway earth station (GES) prior to the real-time channel assignment by the multiple GES's sharing the resources harmoniously. The time-variant nature of those systems implies that a dynamic FTSP planning method is crucial to the operation to cope with the time-variant traffic demand and the inter-beam interference condition. This paper proposes and compares three algorithms (Serial-numbering, DP-based, and Greedy algorithms) mixed with two strategies (concentrated- and spread-types) for the resource allocation. The numerical evaluation demonstrates that Greedy algorithm with the spread-type strategy is very effective and promising with feasible calculation time for the FTSP generation.

In software-based wireless multimedia communications systems, each mobile terminal will be able to select its best-suited transmission format according to its quality of service (QoS) and channel condition. In this paper, we focus attention on "access scheme selectability" in such a software-based system, and discuss the traffic performance improvement due to adaptive access scheme selection. Assuming a software-based TDMA/CDMA system where time division multiple access (TDMA) and direct sequence code division multiple access (DS-CDMA) schemes are flexibly selectable, we evaluate the traffic performance in terms of average delay with a typical multimedia service model to be supported in future wireless communications systems. In the TDMA/CDMA system, how to determine an appropriate access scheme for a user is a key issue. Therefore, we discuss the selection algorithm for efficiently supporting heterogeneous multimedia services. Our computer simulation results show that the software-based system with a simple access scheme selection algorithm can significantly improve the traffic performance as compared with conventional hardware-based systems.

A merged analog-digital circuit architecture is proposed for implementing intelligence in SoC systems. Pulse modulation signals are introduced for time-domain massively parallel analog signal processing, and also for interfacing analog and digital worlds naturally within the SoC VLSI chip. Principles and applications of pulse-domain linear arithmetic processing are explored, and the results are expanded to the nonlinear signal processing, including an arbitrary chaos generation and continuous-time dynamical systems with nonlinear oscillation. Silicon implementations of the circuits employing the proposed architecture are fully described.

This paper deals with a study of a problem for finding the minimum-cost spanning tree with a response-time bound. The relation of cost and response-time is given as a monotonous decreasing and convex function. Regarding communication bandwidth as cost in an information network, this problem means a minimum-cost tree shaped routing for response-time constrained broadcasting, where any response-time from a root vertex to other vertex is less than a given time bound. This problem is proven to be NP-hard and consists of the minimum-cost assignment to a rooted tree and the minimum-cost tree finding. A nonlinear programming algorithm solves the former problem for the globally optimal solution. For the latter problem, different types of heuristic algorithms evaluate to find a near optimal solution experimentally.

This paper proposes three MAC protocols over APON to provide residential and small business customers with multimedia services. The proposed protocols support the frame structure of ITU-T recommendation G.983.1 and also provide diverse ATM service classes such as CBR, rtVBR, nrtVBR, ABR, and UBR traffics. Each service is allocated on the basis of priority. Especially, for allocating CBR and rtVBR services, each protocol uses different cell arrival timing information which is achieved with specific coding and ranging procedure. Focusing the difference of cell arrival timing information, we will investigate the performance of proposed protocols. For the proposed MAC protocols, we present grant field format, minislot format, and bandwidth allocation algorithm. Computer simulation shows the performance of the proposed protocols in terms of CDV and delay, comparing with the normal FIFO protocol.

This paper describes the results of a series of laboratory experiments for performance evaluations of our proposed Maximum Likelihood Sequence Estimation (MLSE) based interference canceller, the Interference Canceling Equalizer (ICE), which can cancel both co-channel interference (CCI) and inter-symbol interference (ISI). To verify the feasibility of ICE for the Japanese cellular communications system, a standard of which has been released under the name of Personal Digital Cellular (PDC) system, a prototype system was constructed using 27 TI TMS320C40 Digital Signal Processor (DSP) chips. The ICE prototype works in real-time on the PDC air interface, major specifications of which are π/4 QDPSK 21 k symbols/s 3-channel time-division multiple-access (TDMA). Two-branch diversity reception is used to enhance the signal detection performance of ICE. In the experiments, BER performances were evaluated using the prototype system. Under a single-path Rayleigh fading and a single CCI condition, the ICE receiver attains the BER of less than 310-2 with the negative values of the average CIR: for fD = 5 Hz and 40 Hz, the average CIR more than -20 dB and -10 dB, respectively. Under a double-path Rayleigh fading and a single CCI condition, the ICE receiver attains the BER of less than 1.510-2 with the negative values of the average CIR: for fD = 5 Hz and 40 Hz, the average CIR more than -20 dB and -10 dB, respectively. The laboratory test results suggest that the ICE receiver has potential for system capacity enhancement.

A 5.6 GOPS/1.4 GFLOPS 350 MHz, four-way very long instruction word (VLIW) microprocessor is developed for embedded applications in a 0.18 µm five-layer-metal CMOS process. This processor features a two-way integer pipeline and two-way floating/media pipelines. Each floating pipeline and media pipeline has two-parallel and four-parallel single instruction multiple-data (SIMD) mechanisms, respectively. The processor has separate instruction and data caches, each of 16 KB in size and having four-way set associative. The data cache employs a non-blocking technique and can process two load instructions in parallel. The processor had about a 50% clock net power reduction compared with one without power optimization. 6.7 million transistors are integrated in an area of 7.5 mm 7.5 mm. Since all circuit blocks were developed using logic synthesis, the processor is easy to adapt to system-on-a-chip (SoC) applications.

A 64-bit architecture for an embedded processor targeted for next-generation digital consumer products has been developed. It has dual-mode instruction sets and is optimized for high multimedia performance, provided by SIMD/floating-point vector instructions in 32-bit length ISA, and small code size, provided by a conventional 16-bit length ISA. Large register files, (6464b and 6432b), a split-branch mechanism, and virtual cache are also adopted in the architecture. A 714MIPS/9.6 GOPS/400 MHz processor core with the 64-bit architecture and a system LSI containing the core are developed using 0.15-µm technology. The LSI includes a 3.2 GB/sec high-bandwidth on-chip bus, a high-speed DRAM interface, a SRAM/Flash/ROM/Multiplexed-bus interface, and a 66 MHz PCI interface that provide the performance required for next-generation multimedia applications.

An aspect of the diverse developments of digital signal processing (DSP) over the last decade are summarized. The current progress of some core fields from the widespread fields are treated in this paper. The selected fields are filter design, wavelet theory and filter bank, adaptive signal processing, nonlinear filters, multidimensional signal processing, intelligent signal processing, and digital signal processor. Through the overview of recent research activities, the interdisciplinary character of the DSP should be proved. Some challenging research direction is described in the last section.

Within the next few decades, high-end telecommunication systems on the larger nationwide network will require a switching capacity of over 5 Tbps. Advanced optical transmission technologies, such as wavelength division multiplexing (WDM) will support optical-fiber data transmission at such speeds. However, semiconductors may not be capable of high-throughput data switching because of the limitations by power consumption and operating speed, and pin count. Superconducting single flux quantum (SFQ) technology is a promising approach for overcoming these problems. This paper proposed an optical-electrical-SFQ hybrid switching system and a novel switch architecture. This architecture uses time-shifted internal speedup, shuffle and grouping exchange and a Batcher-Banyan switch. Our proposed switch consists of an interface circuit with small buffers, a Batcher sorter, a time-shift-speedup buffer (TSSB), a Banyan switch, and a slowdown buffer. Simulations showed good scalability up to 100 Tbps, which no router could ever offer such features.

For distributed multimedia applications, the development of adaptive QoS (quality of service) management mechanisms is needed to guarantee various and changeable end-to-end QoS requirements. In this paper, we propose an adaptive QoS management framework based on multi-agent systems. In this framework, QoS management mechanisms are divided into two phases, the flow establishment and renegotiation phase and the media-transfer phase. An adaptation to system resource changes and various user requirements is accomplished by direct or indirect collaborations of the agents in each phase. In the flow establishment and renegotiation phase, application agents determine optimal resource allocation with QoS negotiations to maximize the total users' utility. In the media-transfer phase, stream agents collaborate to adjust each stream QoS reactively. In addition, personal agents help a novice user to specify stream QoS without any a priori knowledge of QoS. To make the interworking of agents tractable, a QoS mapping mechanism is needed to translate the QoS parameters from level to level, since the expression of QoS differs from level to level. As an example of multimedia application based on the proposed framework, a one-way video system is designed. The experimental results of computer simulation show the validity of the proposed framework.

In this paper we propose a subsequence matching algorithm that supports moving average transform of arbitrary order in time-series databases. Moving average transform reduces the effect of noise and has been used in many areas such as econometrics since it is useful in finding the overall trends. The proposed algorithm extends the existing subsequence matching algorithm proposed by Faloutsos et al. (SUB94 in short). If we applied the algorithm without any extension, we would have to generate an index for each moving average order and would have serious storage and CPU time overhead. In this paper we tackle the problem using the notion of index interpolation. Index interpolation is defined as a searching method that uses one or more indexes generated for a few selected cases and performs searching for all the cases satisfying some criteria. The proposed algorithm, which is based on index interpolation, can use only one index for a pre-selected moving average order k and performs subsequence matching for arbitrary order m ( k). We prove that the proposed algorithm causes no false dismissal. The proposed algorithm can also use more than one index to improve search performance. The algorithm works better with smaller selectivities. For selectivities less than 10-2, the degradation of search performance compared with the fully-indexed case--which is equivalent to SUB94--is no more than 33.0% when one index is used, and 17.2% when two indexes are used. Since the queries with smaller selectivities are much more frequent in general database applications, the proposed algorithm is suitable for practical situations.