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3021-3040hit(3578hit)

  • One-Point Algebraic Geometric Codes from Artin-Schreier Extensions of Hermitian Function Fields

    Daisuke UMEHARA  Tomohiko UYEMATSU  

     
    PAPER-Coding Theory

      Vol:
    E81-A No:10
      Page(s):
    2025-2031

    Recently, Garcia and Stichtenoth proposed sequences of algebraic function fields with finite constant fields such that their sequences attain the Drinfeld-Vl bound. In the sequences, the third algebraic function fields are Artin-Schreier extensions of Hermitian function fields. On the other hand, Miura presented powerful tools to construct one-point algebraic geometric (AG) codes from algebraic function fields. In this paper, we clarify rational functions of the third algebraic function fields which correspond to generators of semigroup of nongaps at a specific place of degree one. Consequently, we show generator matrices of the one-point AG codes with respect to the third algebraic function fields for any dimension by using rational functions of monomial type and rational points.

  • CAM-Based Array Converter for URR Floating-Point Arithmetic

    Kuei-Ming LU  Keikichi TAMARU  

     
    PAPER-Computer Applications

      Vol:
    E81-D No:10
      Page(s):
    1120-1130

    In order to lessen overflow or underflow problem in numerical computation, several new floating-point arithmetics have been proposed. The significant advantage of these new arithmetics is that a number can be represented in a wider range since the fields of exponent and mantissa are changed depending on the magnitude of number. The main issues of these arithmetics are how to find the boundary between exponent and mantissa as well as to convert the formats between new floating-point arithmetic and fixed-point arithmetic quickly. In this paper, a CAM-based array converter based on the Universal Representation of Real number (URR) floating-point arithmetic is described. Using match retrieval device CAM, the detection of the boundary can be accomplished faster than conventional circuits. Arranging the basic cells into iterative array structure, the fast separation/connection operation is achieved. The speed, area and power consumption of the converter is estimated.

  • Fault-Tolerant Adaptive Wormhole Routing in 2D Mesh

    Seong-Pyo KIM  Taisook HAN  

     
    PAPER-Fault Tolerant Computing

      Vol:
    E81-D No:10
      Page(s):
    1064-1071

    A fault-tolerant wormhole routing algorithm on mesh-connected processors is proposed. The proposed algorithm is based on the solid fault model and allows the fault polygons to be overlapped. The algorithm compares the position of fault region relative to current channel with the fault direction field of a misrouted message to route around overlapped fault polygons. A node deactivating algorithm to convert non-solid fault region into solid fault region is also proposed. The proposed routing algorithm uses four virtual channels and is deadlock and livelock free.

  • Two-Step Extraction of Bilingual Collocations by Using Word-Level Sorting

    Masahiko HARUNO  Satoru IKEHARA  

     
    PAPER-Artificial Intelligence and Cognitive Science

      Vol:
    E81-D No:10
      Page(s):
    1103-1110

    This paper describes a new method for learning bilingual collocations from sentence-aligned parallel corpora. Our method comprises two steps: (1) extracting useful word chunks (n-grams) in each language by word-level sorting and (2) constructing bilingual collocations by combining the word-chunks acquired in stage (1). We apply the method to a two kinds of Japanese-English texts; (1) scientific articles that comprise relatively literal translations and (2) more challenging texts: a stock market bulletin in Japanese and its abstract in English. In both cases, domain specific collocations are well captured even if they were not contained in the dictionaries of specialized terms.

  • An Analysis of the Relationship between IDDQ Testability and D-Type Flip-Flop Structure

    Yukiya MIURA  Hiroshi YAMAZAKI  

     
    PAPER-Fault Tolerant Computing

      Vol:
    E81-D No:10
      Page(s):
    1072-1078

    This paper describes IDDQ testability for bridging faults in a variety of flip-flops. The flip-flop is a basic element of the sequential circuit and there are various structures even for the same type. In this paper, we use five kinds of master-slave D-type flip-flops as the circuit under test. Target faults are two-line resistive bridging faults extracted from a circuit layout. A flip-flop with a deliberately introduced bridging fault is simulated by the SPICE simulator. Simulation results show that IDDQ testing cannot detect faults existing at specific points in some flip-flops, and this problem depends on the flip-flop structure. However, IDDQ testing has high fault coverage ( 98%) compared with traditional logic testing. We also examine performances of fully IDDQ testable flip-flops.

  • An Efficient Finite Element-Integral Equation Method for Electromagnetic Scattering from Metallic Cylinders with Arbitrary Cross Sections

    Fengchao XIAO  Hatsuo YABE  

     
    PAPER-Electromagnetic Theory

      Vol:
    E81-C No:10
      Page(s):
    1648-1654

    An efficient finite element-integral equation method is presented for calculating scattered fields from conducting objects. By combining the integral equation solution with the finite element method, this formulation allows a finite element computational domain terminated very closely to the scatterer and thus results in the decrease of the resultant matrix size. Furthermore, we employ a new integral approach to establish the boundary condition on the finite element terminating surface. The expansion of the fields on the integration contour is not related to the fields on the terminating surface, hence we obtain an explicit expression of the boundary condition on the terminating surface. Using this explicit boundary condition with the finite element solution, our method substantially improves the computational efficiency and relaxes the computer memory requirements. Only one matrix inversion is needed through our formulation and the generation and storing of a full matrix is not necessary as compared with the conventional hybrid finite element methods. The validity and accuracy of the formulation are checked by some numerical solutions of scattering from two-dimensional metallic cylinders, which are compared with the results of other methods and/or measured data.

  • A Mixed Upper Bound on the Maximum Size of Codes for Multiple Burst Error Correction and Detection

    Mitsuru HAMADA  

     
    PAPER-Coding Theory

      Vol:
    E81-A No:10
      Page(s):
    1964-1971

    We derive an upper bound on the size of a block code with prescribed burst-error-correcting capability combining those two ideas underlying the generalized Singleton and sphere-packing bounds. The two ideas are puncturing and sphere-packing. We use the burst metric defined by Gabidulin, which is suitable for burst error correction and detection. It is demonstrated that the proposed bound improves previously known ones for finite code-length, when minimum distance is greater than 3, as well as in the asymptotic forms.

  • Design Considerations of Data-Driven Self-Timed RSFQ Adder Circuits

    Nobuyuki YOSHIKAWA  Hiroshi TAGO  Kaoru YONEYAMA  

     
    INVITED PAPER-Digital Applications

      Vol:
    E81-C No:10
      Page(s):
    1618-1626

    We have designed rapid single-flux-quantum (RSFQ) adder circuits using two different architectures: one is the conventional architecture employing globally synchronous clocking and the other is the data-driven self-timed (DDST) architecture. It has been pointed out that the timing margin of the RSFQ logic is very sensitive to the circuit parameter variations which are induced by the fabrication process and the device parameter uncertainty. Considering the physical timing in the circuits, we have shown that the DDST architecture is advantageous for realizing RSFQ circuits operating at very high frequencies. We have also calculated the theoretical circuit yield of the DDST adders and shown that a four-bit system operating at 10 GHz is feasible with sufficient operating margin, considering the present 1 kA/cm2 Nb Josephson technology.

  • Low-Noise Superconducting Receivers for Millimeter and Submillimeter Wavelengths

    Sheng-Cai SHI  Takashi NOGUCHI  

     
    INVITED PAPER-Analog Applications

      Vol:
    E81-C No:10
      Page(s):
    1584-1594

    Millimeter- and submillimeter-wave low-noise superconducting receivers, such as superconductor-insulator-superconductor (SIS) mixers, hot-electron bolometer (HEB) mixers, and superconducting direct detectors, are addressed in this paper. Some general topics on the development of SIS mixers, including SIS junction and integrated tuning circuitry, mixing circuitry, and mixer-performance simulation, are extensively discussed. A tuneless waveguide SIS mixer developed at Nobeyama Radio Observatory (NRO) and its performance are presented. The fundamental mechanisms of diffusion- and phonon-cooled HEB mixers and recent advances in HEB mixers are briefly reviewed. Finally, incoherent detectors with superconducting tunnel junctions are discussed. Results for a direct detecting experiment at 500 GHz are given.

  • On Reducing Complexity of a Soft-Decision Decoding Algorithm for Cyclic Codes Based on Energy Minimization Principle

    Akira SHIOZAKI  Kazutaka AOKI  

     
    PAPER-Coding Theory

      Vol:
    E81-A No:10
      Page(s):
    1998-2004

    We propose a novel soft-decision decoding algorithm for cyclic codes based on energy minimization principle. The well-known soft-decision decoding algorithms for block codes perform algebraic (hard-decision) decoding several times in order to generate candidate codewords using the reliability of received symbols. In contrast, the proposed method defines energy as the Euclidean distance between the received signal and a codeword and alters the values of information symbols so as to decrease the energy in order to seek the codeword of minimum energy, which is the most likely codeword. We let initial positions be the information parts of signals obtained by cyclically shifting a received signal and look for the point, which represents a codeword, of minimum energy by moving each point from several initial positions. This paper presents and investigates reducing complexity of the soft-decision decoding algorithm. We rank initial positions in order of reliability and reduce the number of initial positions in decoding. Computer simulation results show that this method reduces decoding complexity.

  • An Estimation by Interval Analysis of Region Guaranteeing Existence of a Solution Path in Homotopy Method

    Mitsunori MAKINO  

     
    PAPER-Numerical Analysis

      Vol:
    E81-A No:9
      Page(s):
    1886-1891

    Related with accuracy, computational complexity and so on, quality of computing for the so-called homotopy method has been discussed recently. In this paper, we shall propose an estimation method with interval analysis of region in which unique solution path of the homotopy equation is guaranteed to exist, when it is applied to a certain class of uniquely solvable nonlinear equations. By the estimation, we can estimate the region a posteriori, and estimate a priori an upper bound of the region.

  • Assignment of Intervals to Parallel Tracks with Minimum Total Cross-Talk

    Yasuhiro TAKASHIMA  Atsushi TAKAHASHI  Yoji KAJITANI  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E81-A No:9
      Page(s):
    1909-1915

    The most basic cross-talk minimization problem is to assign given n intervals to n parallel tracks where the cross-talk is defined between two intervals assigned to the adjacent tracks with the amount linear to parallel running length. This paper solves the problem for the case when any pair of intervals intersects and the objective is to minimize the sum of cross-talks. We begin the discussion with the fact that twice the sum of lengths of n/2 shortest intervals is a lower bound. Then an interval set that attains this lower bound is characterized with a simple assignment algorithm. Some additional considerations provide the minimum cross-talk for the other interval sets. The main procedure is to sort the intervals twice with respect to the length of left and right halves of intervals.

  • An Improved Recursive Decomposition Ordering for Higher-Order Rewrite Systems

    Munehiro IWAMI  Masahiko SAKAI  Yoshihito TOYAMA  

     
    PAPER-Automata,Languages and Theory of Computing

      Vol:
    E81-D No:9
      Page(s):
    988-996

    Simplification orderings, like the recursive path ordering and the improved recursive decomposition ordering, are widely used for proving the termination property of term rewriting systems. The improved recursive decomposition ordering is known as the most powerful simplification ordering. Recently Jouannaud and Rubio extended the recursive path ordering to higher-order rewrite systems by introducing an ordering on type structure. In this paper we extend the improved recursive decomposition ordering for proving termination of higher-order rewrite systems. The key idea of our ordering is a new concept of pseudo-terminal occurrences.

  • Plastic Cell Architecture: A Scalable Device Architecture for General-Purpose Reconfigurable Computing

    Kouichi NAGAMI  Kiyoshi OGURI  Tsunemichi SHIOZAWA  Hideyuki ITO  Ryusuke KONISHI  

     
    PAPER

      Vol:
    E81-C No:9
      Page(s):
    1431-1437

    We propose an architectural reference of programmable devices that we call Plastic Cell Architecture (PCA). PCA is a reference for implementing a device with autonomous reconfigurability, which we also introduce in this paper. This reconfigurability is a further step toward new reconfigurable computing, which introduces variable- and programmable-grained parallelism to wired logic computing. This computing follows the Object-Oriented paradigm: it regards configured circuits as objects. These objects will be described in a new hardware description language dealing with the semantics of dynamic module instantiation. PCA is the fusion of SRAM-based FPGAs and cellular automata (CA), where the CA are dedicated to support run time activities of objects. This paper mainly focus on autonomous reconfigurability and PCA. The following discussions examine a research direction towards general-purpose reconfigurable computing.

  • Information Integration Architecture for Agent-Based Computer Supported Cooperative Work System

    Shigeki NAGAYA  Yoshiaki ITOH  Takashi ENDO  Jiro KIYAMA  Susumu SEKI  Ryuichi OKA  

     
    PAPER

      Vol:
    E81-D No:9
      Page(s):
    976-987

    We propose an information integration architecture for a man-machine interface to construct a new agent-based Computer Supported Cooperative Work (CSCW) system. The system acts as a clerk in cooperative work giving users the advantage of using cooperative work space. The system allows users to do their work in the style of an ordinary meeting because spontaneous expressions of speech and gestures by users are detected by sensors so that they can be integrated with a task model at several levels to create suitable responses in a man-machine interface. As a result, users can dedicate themselves to mutually understand other meeting members with no awareness of direction to the CSCW system. In this paper, we describe the whole system and its information integration architecture for the man-machine interface including, the principle of functions, the current status of the system and future directions.

  • Network Access Control for DHCP Environment

    Kazumasa KOBAYASHI  Suguru YAMAGUCHI  

     
    PAPER-Communication Networks and Services

      Vol:
    E81-B No:9
      Page(s):
    1718-1723

    In the IETF, discussions on the authentication method of the Dynamic Host Configuration Protocol (DHCP) message are active and several methods have been proposed. These related specifications were published and circulated as the IETF Internet-Drafts. However, they still have several drawbacks. One of the major drawbacks is that any user can reuse addresses illegally. A user can use an expired address that was allocated to a host. This kind of "illegal use" of the addresses managed by the DHCP server may cause serious security problems. In order to solve them, we propose a new access control method to be used as the DHCP message authentication mechanism. Furthermore, we have designed and developed the DAG (DHCP Access Control Gateway) according to our method. The DAG serves as a gateway that allows only network accesses from clients with the address legally allocated by the DHCP server. This provides secure DHCP service if DHCP servers do not have an authentication mechanism, which is most likely to occur. If a DHCP server has such an authentication scheme as being proposed in IETF Internet-Draft, the DAG can offer a way to enable only a specific client to access the network.

  • Locating Fold Bifurcation Points Using Subspace Shooting

    Hidetaka ITO  Akira KUMAMOTO  

     
    PAPER-Chaos, Bifurcation and Fractal

      Vol:
    E81-A No:9
      Page(s):
    1791-1797

    A numerical method is proposed for efficiently locating fold bifurcation points of periodic orbits of high-dimensional differential-equation systems. This method is an extension of the subspace shooting method (or the Newton-Picard shooting method) that locates periodic orbits by combining the conventional shooting method and the brute-force method. Fold bifurcation points are located by combining a variant of the subspace shooting method with a fixed parameter value and the secant method for searching the parameter value of the bifurcation point. The target in the subspace-shooting part is an (not necessarily periodic) orbit represented by a Poincare mapping point which is close to the center manifold and satisfies the eigenvalue condition for the bifurcation. The secant-search part finds the parameter value where this orbit becomes periodic. Avoiding the need for differentiating the Poincare map with respect to the bifurcation parameter and exploiting several properties of the center manifold, the proposed method is both robust and easy to implement.

  • A Fast Algorithm for Spatiotemporal Pattern Analysis of Neural Networks with Multivalued Logic

    Hiroshi NINOMIYA  Atsushi KAMO  Teru YONEYAMA  Hideki ASAI  

     
    PAPER-Neural Networks

      Vol:
    E81-A No:9
      Page(s):
    1847-1852

    This paper describes an efficient simulation algorithm for the spatiotemporal pattern analysis of the continuous-time neural networks with the multivalued logic (multivalued continuous-time neural networks). The multivalued transfer function of neuron is approximated to the stepwise constant function which is constructed by the sum of the step functions with the different thresholds. By this approximation, the dynamics of the network can be formulated as a stepwise constant linear differential equation at each timestep and the optimal timestep for the numerical integration can be obtained analytically. Finally, it is shown that the proposed method is much faster than a variety of conventional simulators.

  • Nomadic Computing Environment Employing Wired and Wireless Networks

    Toshiaki TANAKA  Masahiro MORIKURA  Hitoshi TAKANASHI  

     
    INVITED PAPER

      Vol:
    E81-B No:8
      Page(s):
    1565-1573

    This paper presents an integrated network configuration of wired and wireless access systems for nomadic computing and discusses the virtual LAN on a wireless access system. Furthermore, different types of ad hoc networks are summarized to delineate nomadic computing styles. In terms of user mobility, the integrated network provides a seamless connection environment, so a user can move between wireless and wired networks without dropping data communication sessions. This function is critical for nomadic computing users. By defining the integrated network and employing a virtual LAN, a nomadic computing environment can be realized. This paper reviews the key issues to realize integrated networks. They are mobile management including mobile IP, virtual IP and Logical Office, a high performance MAC, and security control.

  • Selection Strategies for Small Targets and the Smallest Maximum Target Size on Pen-Based Systems

    Xiangshi REN  Shinji MORIYA  

     
    PAPER-Computer Systems

      Vol:
    E81-D No:8
      Page(s):
    822-828

    An experiment is reported comparing six pen input strategies for selecting a small target using five diffenent sized targets (1, 3, 5, 7 and 9 dot diameter circles respectively, 0. 36 mm per dot). The results showed that the best strategy, in terms of error rate, selection time and subjective preferences, was the "land-on2" strategy where the target is selected when the pen-tip touches the target for the first time after landing on the screen surface. Moreover, "the smallest maximum size" was determined to be 5 dots (1. 8 mm). This was the largest size among the targets which had a significant main effect on error rate in the six strategies. These results are important for both researchers and designers of pen-based systems.

3021-3040hit(3578hit)