Error locating codes were first presented in 1963 by J.K. Wolf and B.Elspas. Since then several code design methods have been proposed. However, their algebraic structure has not yet been clarified. It is apparent that necessary and sufficient conditions for error correcting/detecting codes can be expressed by Hamming distance, but, on the other hand, those for error locating codes cannot always be expressed only by Hamming distance. This paper presents necessary and sufficient conditions for error locating codes by using a newly defined metric and a function. The function represents the number of bytes where Hamming distance between corresponding bytes of two codewords has a certain integer range. These conditions show that an error locating code having special code parameters is an error correcting/detecting code. This concludes that error locating codes include existing bit/byte error correcting/detecting codes in their special cases.

In this paper a new class of single error-correcting fixed block-length (d, k) codes has been proposed. The correctable error types are peak-shift error, insertion or deletion error, symmetric error, etc. The basic technique to construct codes is a systematic construction algorithm of multilevel sequences with a constant Lee weight (TALG algorithm). The coding rate and efficiency are considerably good, and hence the proposed new codes will be very useful for improving the reliability of high density magnetic recording.

We propose a method to search all the zeros of a complex function in a given compact region D Cn. The function f: Cn Cn to be considered is assumed to consist of polynomial and transcendental terms and to satisfy f (x) Rn for any x Rn. Using the properties of such a complex function, we can compute the number of zeros and determine the starting points of paths on the boundary of D, which attain all the zeros of f in D without encountering a singular point. A piecewiselinear approximation of the function on a triangulation is used for both computing the number of zeros and following the paths.

In this paper, we propose a new multicast routing algorithm for constructing the delay-constrained minimal spanning tree in the VP-based ATM networks, in which we consider the efficiency even in the case where the destination dynamically joins/departs the multicast connection. For constructing the delay-constrained spanning tree, we first generate a reduced network consisting of only VCX nodes from a given ATM network, originally consisting of VPX/VCX nodes. Then, we obtain the delay-constrained spanning tree with a minimal tree cost on the reduced network by using our proposed heuristic algorithm. Through numerical examples, we show that our dynamic multicast routing algorithm can provide an efficient usage of network resources when the membership nodes frequently changes during the lifetime of a multicast connection, while the existing multicast routing algorithm may be useful for constructing the multicast tree with a static nature of destination nodes. We also demonstrate that more cost-saving can be expected in dense networks when applying our proposed algorithm.

This paper deals with two different quantitative inversion algorithms for reconstructing the complex permittivity profile of bounded inhomogeneous objects from measured scattered field data. The first algorithm involves an imaging method with single frequency excitation and multiincidence illumination and the second algorithm involves a method with synthetic pulse (multifrequency mode) excitation for objects surrounded by freespace or buried in stratified half-space media. Transmission or reflection imaging protocols are considered depending on aimed applications: microwave imaging in free-space from far-field data for target identification, microwave imaging from near-field data for nondestructive testing (NDT), microwave tomography of buried objects for mine detection and localization, civil engineering and geophysical applications. And Edge-Preserving regularization scheme leading to a significant enhancement in the image reconstructions is also proposed. The methods are illustrated with synthetic and experimental data.

In circuit simulation, dc operating points of nonlinear circuits are obtained by solving circuit equations. In this paper, we consider "hybrid equations" as the circuit equations and discuss the stability of dc operating points obtained by solving hybrid equations. We give a simple criterion for identifying unstable operating points from the information of the hybrid equations. We also give a useful criterion for identifying initial points from which homotopy methods coverge to stable operating points with high possibility. These results are derived from the theory of dc operating point stability developed by M. M. Green and A. N. Willson, Jr.

We propose an on-line writer verification method to improve the reliability of verifying a specific system user. Most of the recent research focus on signature verification especially in the field of on-line writer verification. However, signature verification has a serious problem in that it will accept forged handwriting. To overcome this problem, we have introduced a text-indicated writer verification method. In this method, a different text including ordinary characters is used on every occasion of verification. This text can be selected automatically by the verification system so as to reflect the specific writer's personal features. A specific writer is accepted only when the same text as indicated by the verification system is inputted, and the system can verify the writer's personal features from the inputted text. Moreover, the characters used in the verification process can be different from those in the enrolment process. This method makes it more difficult to get away with forged handwriting than the previous methods using only signatures. We also discuss the reliability of the proposed method with some simulation results using handwriting data. From these simulation results, it is clear that this method keeps high reliability without the use of signatures.

In VLSI and printed wiring board design, routing process usually consists of two stages: the global routing and the detailed routing. The routability checking is to decide whether the global wires can be transformed into the detailed ones or not. In this paper, we propose two graphs, the capacity checking graph and the initial flow graph, for efficient routability checking in planar layouts.

We have previously proposed a scannable memory configuration which is useful in testing logic blocks around memory arrays. Although the configuration is supposed to be effective in testing the memory array itself by its frequent read/write access during the scan operation, it has not been theoretically shown what types of faults can be detected. In this paper, from a viewpoint of memory testing, we investigate the testability of the scannable memory configuration and propose a memory array test using the scan path. It is shown that we can detect (1) all stuck-at faults in memory cells, (2) all stuck-at faults in address decoders, (3) all stuck-at faults in read/write logic, (4) static, dynamic and 2-coupling faults between memory cells of adjacent words, and (5) static coupling faults between memory cells in the same word. The test can be accomplished simply by comparing scan-in data and scan-out data. The test vector is 20ms bit long, where m is the number of words of the memory array under test and s is the total scan path length.

A parallel IP router that uses off-the-shelf wor-kstations and interconnecting switches is presented. This router, called CORErouter-I, is a medium-grained, functionally distributed parallel system consisting of four kinds of processors for routing, routing-table searching, servicing, and line interfacing. Also discussed are issues related to the implementation of CORErouter-I, especially in terms of routing protocol processing and packet-forwarding. Performance characteristics of CORErouter-I are also clarified through several experiments performed to evaluate maximum throughput, analyze packet-forwarding time, and estimate the effect of parallel processing on the route-flapping problem.

This study shows the results of evaluating the flux noises at low frequency when the alternating current(AC) bias direct offset integrated technique(DOIT) with additional positive feedback (APF) is used in a high-Tc dc superconducting quantum interference device (SQUID). The AC-bias DOIT can reduce low-frequency noise without increasing the level of white noise because each operating point in the two voltage-flux characteristics with AC bias can always be optimum on the magnetometer in the high-Tc dc-SQUID. APF can improve the effective flux-to-voltage transfer function so that it can reduce the equivalent flux noise due to the voltage noise of the preamplifier in the magnetometer. The use of APF combined with the AC-bias DOIT reduced the noise of the magnetometer by factors of 1.5 (33µΦ0/Hz vs. 50 µΦ0/Hz) at100 Hz, 3.5 (43 µΦ0/Hz vs. 150 µΦ0/Hz) at 10 Hz, and 5.2 (67 µΦ0/Hz vs. 351 µΦ0/Hz) at 1 Hz as compared with the noise levels that were obtained with the static-current-bias DOIT. The contribution of the factors at 1 Hz is about 2 by APF and 2.6 by AC bias. The performance of improving the flux noise in the AC -bias DOIT with APF is almost equal to that of the flux locked loop (FLL) circuits in which the flux modulation uses a coupling system with a transformer and with the AC bias.

New THz radiation devices made of high-Tc superconductors are fabricated and their characteristics are studied in detail. Ultrashort electromagnetic pulses with 0.5 ps width have been radiated into free space from current biased devices made of superconducting YBa2Cu3O7 (YBCO) films by exciting with femtosecond laser pulses. The Fourier spectrum of them extends up to 3 THz. The radiation mechanism is ascribed to the ultrafast supercurrent modulation by the optical pulses. The THz waveform is analyzed using rate equations describing the relaxation of photoexcited quasiparticles. By the improvement of the device structure and the collecting optics, the radiation power can be increased up to 0.5 µW. A new type THz radiation from YBCO films under an external magnetic field without a transport current is also reported.

A 90 GHz band planar-type superconducting mixer using Ba1-xKxBiO3 (BKBO) bicrystal junctions was fabricated on a MgO bicrystal substrate. The mixer is integrated with microwave circuits and two junctions, but we could not operate the mixer in image rejection mode because of process damage to the junction properties. However we confirmed the mixing operation; the intermediate frequency (IF) signal was observed up to 17K (LO87 GHz, RF92 GHz).

In this paper we analyze the properties of regular segmentation schemes for 2-D Field Programmable Gate Arrays (FPGAs). Such schemes can be viewed as generalization of the Xilinx-like wire segmentations. We discuss their routing properties and propose a new FPGA design concept of applying architectural coupling to improve chip routability. We give the experimental routing results of such architectures for justification.

Logic operations in principle have been demonstrated based on the planar high-Tc Superconducting QUantum Interference Device (SQUID). Two kinds of logic gates were produced by using the focused ion beam (FIB) superconducting weak links fabricated in NdBa2Cu3O7-δ (NBCO) thin films. Logic gates investigated in this paper are (1) an rf-SQUID based logic gate which utilizes threshold characteristics, and (2) a dc-SQUID based logic gate which is an elementary gate of RSFQ circuits. Elementary logic operation such as (1) AND/OR logic and (2) SET-RESET flip-flop operation were successfully obtained in the logic gates. In addition to the present experimental results, some problems and future prospects are also discussed.

In layout design of transport-processing FPGAs, it is required that not only routing congestion is kept small but also circuits implemented on them operate with higher operation frequency. This paper extends the proposed simultaneous placement and global routing algorithm for transport-processing FPGAs whose objective is to minimize routing congestion and proposes a new algorithm in which the length of each critical signal path (path length) is limited within a specified upper bound imposed on it (path length constraint). The algorithm is based on hierarchical bipartitioning of layout regions and LUT (Look Up Table) sets to be placed. In each bipartitioning, the algorithm first searches the paths with tighter path length constraints by estimating their path lengths. Second the algorithm proceeds the bipartitioning so that the path lengths of critical paths can be reduced. The algorithm is applied to transport-processing circuits and compared with conventional approaches. The results demonstrate that the algorithm satisfies the path length constraints for 11 out of 13 circuits, though it increases routing congestion by an average of 20%. After detailed routing, it achieves 100% routing for all the circuits and decreases a circuit delay by an average of 23%.

In this paper, we propose a scalable service networking architecture as a TINA-like environment for providing flexibly various mobility services. The proposed architecture provides an environment that enables the advent of service providers and rapidly introduces multimedia applications, considering networks scalability. For supporting customized mobility services, this architecture adopts a new service component, which we call Omnipresent Personal Environment Manager (OpeMgr). In order to support mobile users who move between heterogeneous networks, for instance, between the TINA-like environment and the Internet environment, we propose a structure of a gateway. In addition, the proposed architecture uses the fixed and mobile agent approaches for supporting the user's mobility, and we evaluated their performances with comparing those approaches.

A non-isothermal device simulation, consisting of solving heat flow equation three-dimensionally together with other semiconductor equations two-dimensionally, is reported for various arrangements of a pluralty of transistors mounted on a single chip. These arrangements are intended to simulate the real situation in an IC chip whereas a three-dimensional solution of the heat flow equation is aimed at accurately determining the thermal interdependence among individual transistors. As a result, the drain current versus drain voltage characteristics of a miniaturized transistor is found to exhibit a heat-induced negative resistance region.

A Unique Input/Output (UIO) sequence for the state J of a protocol is a sequence of input/output pairs that is unique to state J. Obtaining UIO sequences from the protocol specification is a very important problem in protocol conformance testing. Let n and m be the total number of states and transitions of the protocol, respectively, and dmax be the largest outdegree of any state, W. Chun and P. D. Amer proposed an O(n2(dmax)2n-1) algorithm to obtain the minimum-length UIO sequences (where the length refers to the number of input/output pairs). However, n and m are normally very large for real protocols. In this paper, we propose an O(n*m) algorithm for obtaining UIO sequences. In theory, our algorithm yields a UIO sequence which contains at most n1 input/output pairs. In experimentation, ten protocol examples collected from recent papers, the ISO TP0 protocol, the ISDN Q. 931 network-side protocol, and the CCITT X. 25 protocol show that in average the obtained UIO sequences are only 11.8% longer than the minimum-length ones, and 97.4% of the existent UIO sequences can be found. And our algorithm is extended for minimizing the cost of UIO sequences and for obtaining synchronizable UIO sequences, which have not been achieved by any algorithm proposed earlier.

Distributed multimedia applications are often sensitive to the Quality of Service (QoS) provided by the communication network. They usually require guaranteed QoS service, so that real-time communication is possible. However, searching a route with multiple QoS constraints is known to be a NP-complete problem. In this paper, we propose a new simple and efficient distributed QoS routing algorithm, called "DQoSR," for supporting real-time communication in high-speed networks. It searches a route that could guarantee bandwidth, delay, and delay jitter requirements. Routing decision is based only on the modified cost, hop and delay vectors stored in the routing table at each node and its directly connected neighbors. Moreover, DQoSR is proved to construct loop-free routes. Its worst case message complexity is O(|V|2), where |V| is the number of nodes in the network. Thus DQoSR is fast and scales well to large networks. Finally, extensive simulations show that average rate of establishing successful connection of DQoSR is very near to optimum (the difference is less than 0.4%).