This paper presents a 4-valued content-addressable memory (CAM) for fully parallel template-matching operations in real-time cellular logic image processing with fixed templates. A universal literal is essential to perform a multiple-valued template-matching operation. It is decomposed of a pair of a threshold operation in a CAM cell and a logic-value conversion shared by CAM cells in the same column of a CAM cellular array, which makes a CAM cell function simple. Since a threshold operation together with a 4-valued storage element can be designed by using a single floating-gate MOS transistor, a high-density 4-valued universal-literal CAM with a single-transistor cell can be implemented by using a multi-layer interconnection technology. It is demonstrated that the performance of the proposed CAM is much superior to that of conventional CAMs under the same function.

A digital neuro chip with proliferating neuron architecture is described. This chip simulates a neural network model called the adaptive segmentation of quantizer neuron architecture (ASQA). It has proliferating neurons, and can automatically form the optimum network structure for recognition according to the input data. To develop inexpensive commercial hardware and implement a proliferating neuron architecture, we adopt a virtual neuron system for hardware implementation. Namely, this chip is implemented with only an arithmetic unit for network computations, and the network information such as network structure, synaptic weights and so on, are stored in external memories. We devise our original architecture which can efficiently memorize the network information, and moreover, construct a structured network using the ASQA model. As a result, we can recognize about 3,000 Kanji characters using a single chip and a recognition speed of 4.6 msec/character is achieved on a PC.

The computers are connected with each other by the network as a result of the progress of technology in the field of the computer and network, and then all of the data to be processed are transferred quickly and at the real-time through the computer network. However the user can use the computer system at any time, the user must go to the location of the computer system to use the computer resources. The necessities for using the computer system occur anywhere and anytime in spite of the location of the computer system. For this requirement the mobile computing environment (MCE) is expected strongly. In this paper we introduce the model of MCE and discuss the need of the user authentication at entering and logging-in the network in MCE only with a user ID. We propose the method of a user ID assignment from which a server ID can be decided by a simple logical operation. Also, we propose a protocol for a user authentication in MCE and discuss the robustness of security against the various attacking on the route.

Conformance testing is to see if the protocol implementation conforms to its specification. A lot of test sequences have been developed for testing centers. Yet directly applying these test sequences to the simple testing system in laboratories suffers from the frequently-occurred synchronization problems. This paper proposes a new technique to disconnect a test sequence into segments based on their functions, and reconnects them into a new test sequence that simulates these functions yet suffers less from the synchronization problems.

We present a new method for the adaptive control of nonminimum phase continuous-time systems based on the pole-zero placement using approximate inverse systems to avoid the unstable pole-zero cancellations. Using this method effect of the unstable zeros cab be compensated approximately. We show how unstable pole-zoro cancellations can be avoided, and that this method has the advantage of being able to determine an approximate inverse system independently of the plant zeros. The proposed scheme uses only the available input and output data and the stability using approximate inverse systems is analyzed. Finally, the results of computer simulation are presented to illustrate the effectiveness of the proposed method.

A new method is proposed for generating synchronizable test sequences which can be applied in the distributed test architecture for protocol conformance testing. The method consists of a duplex digraph technique and a rural Chinese postman tour algorithm to generate a minimum-length synchronizable test sequence using distinguishing sequences.

We have developed a management agent that adapts the delegation concept to achieve efficient network management. In conventional delegation architecture, a network management operator details management operations in an operation-script that describes management operation flow and such network management functions as event management and path tracing. The operator sends this script to agents to execute. In our delegation architecture, the operator sends only a script skeleton describing management operation flow alone; management functions are built into the agents in the form of fuction objects. This helps keep management traffic low. Each function object is designed by utilizing three operational objects: enhanced, primitive, and communication. Each enhanced operational object (EOO) provides a script skeleton with an individual network management function. A primitive operational object (POO) provides an EOO with managed object (MO) access functions. A communication operational object (COO) provides an EOO with a mechanism for accessing the functions of other remote EOOs. We have tested our design by applying it to a path tracing application, and we have measured the total data transfer size between a manager and an agent and the amount of memory usage in our agent's running environment. Evaluation of our implementation suggests that our design can be applied such network management functions as connection establishment and release, fault isolation, and service provisioning.

We have been studying on subthreshold characteristics of SOI (Silicon-On-Insulator) MOSFET's in terms of substrate bias dependence using a one-dimensional subthreshold device simulator based on Poisson equation in an SOI multilayer structure for estimating structural parameters of real devices. Here, we consider the quantum mechanical effects in the electron inversion layer of thin SOI MOSFET's, such as the two-dimensionally quantized electron states and transports, with a self-consistent solver of Poisson and Schrodinger equations and a mobility model by the relaxation time approximation. From results of simulations, we found a significant difference between this model and the classical model and concluded that the quantum mechanical effects need to be considered in analizing thin-film SOI devices.

This paper describes the effectiveness of stream-oriented data-driven scheme for achieving autonomous fault management of hyper-distributed systems such as networks based on the Telecommunications Information Networking Architecture (TINA). TINA, whose specifications are in the finalizing phase within TINA-Consortium, is aiming at achieving interoperability and reusability of telecom applications software and independent of underlying technologies. However, to actually implement TINA network, it is essential to consider the technology constraints. Especially autonomous fault management at run-time is crucial for distributed network environment because centralized control using global information is very difficult. So far many works have been done on so-called off-line management but runtime management of service failure seems immature. This paper proposes introduction of stream-oriented data-driven processors to the autonomous fault management at runtime in TINA based distributed network environment. It examines the features of distributed network applications and technology requirements to achieve fault management of those distributed applications such as effective multiprocessing of surveillance, testing, reconfiguration in addition to ordinary processing.

Dynamic Term Rewriting Calculus is a new computation model proposed by the authors for the purpose of formal description and verification of algorithms treating Term Rewriting Systems. The computation of DTRC is basically term rewriting. The characteristic features of DTRC are dynamic change of rewriting rules during computation and hierarchical declaration of not only function symbols and variables but also rewriting rules. These features allow us to program metacomputation of TRSs in DTRC, that is , we can implement in DTRC in a natural way those algorithms which manipulate term rewriting systems as well as those procedures which verify such algorithms. In this paper, we give a formal description of DTRC. We then show some results on confluence property of DTRC.

Silica-based planar lightwave circuits (PLCs) are reviewed in terms of WDM applications. Four types of basic multiplexer are described and compared. Some topical applications of these multiplexers are introduced with their WDM systems. We conclude that because of these various applications, silica-based PLCs will play an important role in future WDM systems.

Recently, a wavelength division multi/demultiplexing system has been viewed with keen interest because it is possible to increase the transmission capacity and system flexibility. An arrayed waveguide grating (AWG) type of Multi/demultiplexer which is one of the key components to realize such a system has been developed by using Planar Lightwave Circuits (PLCs). Newly designed optical circuits have been incorporated into the AWG to control the center wavelength and to expand the pass band width. The 3 dB pass band width is 1.4 times that of a conventional AWG. It is confirmed that the newly developed AWG has low polarization dependence, low temperature dependence and high reliability.

In this paper, we propose a new strategy of estimating correlation dimensions in combination with the method of surrogate data, which is a kind of statistical control usually introduced to avoid spurious estimates of nonlinear statistics, such as fractal dimensions, Lyapunov exponents and so on. In the case of analyzing time series with the method of surrogate data, it is desirable to decide values of estimated nonlinear statistics of the original data and surrogate data sets as exactly as possible. However, when dimensional analysis is applied to possible attractors reconstructed from real time series, it is very dangerous to decide a single value as the estimated dimensions and desirable to analyze its scaling property for avoiding spurious estimates. In order to solve this defficulty, a dimension estimator algorithm and the method of surrogate data are combined by introducing Monte Carlo hypothesis testing. In order to show effectiveness of the new strategy, firstly artificial time series are analyzed, such as the Henon map with additive noise, filtered random numbers and filtered random numbers transformed by a static monotonic nonlinearity, and then experimental time series are also examined, such as wolfer's sunspot numbers and the fluctuations in a farinfrared laser data.

A high-performance microprocessor-compatible small size full CMOS SRAM cell technology for under 1.8-V operation has been developed. Less than 1-µm spacing between the n and pMOSFETs is achieved by using a retrograde well combined with SSS-OSELO technology. To connect the gates of a driver nMOSFET and a load pMOSFET directly, a 0.3-µm n-gate load pMOSFET, formed by amorphous-Si-film through-channel implantation, is merged with a 0.25-µm p-gate pMOSFET for the peripheral circuits. The memory cell area is reduced by using a mask-free contact process for the local interconnect, which includes titanium-nitride wet-etching using a plasma-TEOS silicone-dioxide mask. The newly developed memory cell was demonstrated using 0.25-µm CMOS process technology. A 6.93-µm2 and 1-V operation full CMOS SRAM cell with a high-performance circuit was achieved by a simple fabrication process.

Term Rewriting System (TRS) is a model of computation and it is used in various application such as algebraic specification. TRS has an inherent concurrency and it is suitable for parallel computing. We have already proposed BOB (Bundle Of Branches), which is a mechanism of data management for parallel rewriting. We have proposed a model of parallel rewriting using BOB and implemented a TRS simulator based on this model on a shared memory parallel computer. Because it fully depends on the feature of a shared memory architecture, that is, a process can access any memory element, it is hard to transport it on a distributed memory parallel computer. In this paper, we propose autonomous BOB model. This model is suitable for a distributed memory architecture since a process uses message passing protocol and the method of load balancing is provided. We implement a TRS simulator using this model on a distributed memory architecture and it runs about 30 times faster on 64 processors than on a single processor.

A highly reliable network which can restore itself from network failures is one important concept for the future high capacity broadband network. In such self-healing network, flooding based failure-restoration algorithm is used to locate new routes and then to reroute failure traffic to that routes automatically when network failures such as link or node failures occur. Since the speed of this algorithm is degraded by the large amount of restoration messages produced by the process, such large volume messages should be reduced. In this paper, the scheme will be proposed, which reduces the large volume messages and efficiently selects alternative routes. In this scheme, the Message Wall will be used to filter useless restoration messages at the tandem nodes and Multi-Message Selecting method will be used to rapidly select a group of link-disjointed alternative routes from the feasible ones in each Flooding Wave sequence. The simulation results show that restoration messages are dramatically reduced and adequate alternative routes can be quickly found out.

We present a general framework with which we can evaluate the flexibility and efficiency of various replay systems for parallel programs. In our approach, program monitoring is modeled by making a virtual dataflow program graph, referred to as a VDG, that includes all the instructions executed by the program. The behavior of the program replay is modeled on the parallel interpretation of a VDG based on two basic parallel execution models for dataflow program graphs: a data-driven model and a demand-driven model. Previous attempts to replay parallel programs, known as Instant Replay and P-Sequence, are also modeled as variations of the data-driven replay, i.e. the datadriven interpretation of a VDG. We show that the demand-driven replay, i.e. the demand-driven interpretation of a VDG, is more flexible in program replay than the data-driven replay since it allows better control of parallelism and a more selective replay. We also show that we can implement a demand-driven replay that requires almost the same amount of data to be saved during program monitoring as does the data-driven replay, and which eliminates any centralized bottleneck during program monitoring by optimizing the demand propagation and using an effective data structure.

We conducted research and development of Distributed Supercomputing Environment (DSE) based on distributed shared memory model to serve as a cluster computing environment to provide parallel processing facilities. Shared memory model and message passing model are well-known typical models of parallel processing. It is desired that hybrid programming environment will make the best use of the prominent features of both models. Consequently, we add a new message passing mechanism to present DSE, and create a prototype called Hybrid DSE as a hybrid model based cluster computing environment. In this paper, we describe the implementation of a message passing mechanism on DSE and performance evaluation of Hybrid DSE.

A novel technique is proposed to fabricate a chirped fiber Bragg grating utilizing thermal diffusion of core dopant. The chirped grating is written with a uniform period by using UV exposure technique in the fiber whose effective index of the guided mode varies along its length. Thermal diffusion of the core dopant it employed to realize this change of the effective index. Through the thermal diffusion process, the effective index of the fiber decreases from its initial value. When the grating is written in the diffused core region, its reflection wavelength becomes shorter than that in the non-diffused region. The continuous change of effective index is required for making a chirped grating. The fiber is heated by a non-uniform heat source. When the uniform grating is written in this region, the reflection wavelength smoothly changes along the fiber length although the grating period is constant. By optimizing the fiber parameters to realize a highly chirped grating, we have obtained a typical one whose bandwidth is 14.1 nm at half maximum and maximum rejection in transmission is 29 dB. Additionally, the proposed method has an advantage to control the chirp profile with high mechanical reliability.

Topological sorting is, given with a directed acyclic graph G = (V, E), to find a total ordering of the vertices such that if (u, v) E then u is ordered before v. Instead of finding total orderings, we wish to find out how many total orderings exist in a given directed acyclic graph G = (V, E). Here we call a total ordering as legal sequence and the problem as legal sequence number problem. In this paper, we first propose theorems on equivalent transformation of graphs with respect to legal sequence number. Then we give a formula to calculate legal sequence number of basic series-parallel digraphs and a way of the calculation for general series-parallel digraphs. Finally we apply our results to show how to obtain legal sequence number for a class of extended series-parallel digraphs.