This paper presents a routing methodology and a routing algorithm used in designing Gb/s LSIs with deep-submicron technology. A routing method for controlling wire width and spacing is adopted for net groups classified according to wire length and maximum-allowable-delay constraints. A high-performance router using this method has been developed and can handle variable wire widths, variable spacing, wire shape control, and low-delay routing. For multi-terminal net routing, a modification of variable-cost maze routing (GVMR) is effective for reducing wire capacitance (net length) and decreasing net delay. The methodology described here has been used to design an ATM-switch LSI using 0. 25-µm CMOS/SIMOX technology. The LSI has a throughput of 40 Gb/s (2. 5 Gbps/pin) and an internal clock frequency of 312 MHz.

We developed a glass ferrule fiber optic connector. During development, we also studied wear-resistant coating technology for preventing scratches on the surface of a glass ferrule. The method of coating was sputtering, and the material was alumina. We confirmed that a thin uniform coating could be formed on the ferrule surface to improve the durability of glass ferrule connectors.

A large-scale modular multicast ATM switch based on a three-stage Clos network architecture is proposed and its performance is studied in this paper. The complexity of our proposed switch is NN if the switch size is NN. The first stage of the proposed multicast switch consists of n sorting modules, where n=N. Each sorting module has n inputs and n outputs and is responsible for traffic distribution. The second and third stages consist of modified Knockout switches which are responsible for packet replication and switching. Although it is a multipath network, cell sequence is preserved because only output buffers are used in this architecture. The proposed multicast switch has the following advantages: 1) it is modular and suitable for large scale deployment; 2) no dedicated copy network is required since copying and switching are performed simultaneously; 3) two-stage packet replication is used which gives a maximum fan-out of n2; 4) translation tables are distributed which gives manageable table sizes; 5) high throughput performance for both uniform and nonuniform input traffic; 6) self-routing scheme is used. The performance of the switch under uniform and non-uniform input traffic is studied and numerical examples demonstrate that the cell loss probability is significantly improved when the distribution network is used. In a particular example, it is shown that for the largest cell loss probability in the second stage to be less then 10-11, the knockout expander, with the use of the distribution network, needs only be larger than 6. On the other hand, without the distribution network, the knockout expander must be larger than 13.

This paper proposes implementation methods of fast ATM layer protection switching function. The main problem in attaining fast ATM protection is the number of connections in one transmission path. The transmission delay of the signal for protection negotiation procedure is relatively less than the processing time in the end nodes. Therefore shortening of the processing time in the nodes is a crucial factor for fast rerouting. This paper focuses on this point and presents some suitable implementations on ATM nodes for fast protection switching. These architectures can attain protection time of less than 50 ms after the detection of a failure at an end node. The key is load-sharing of the hardware and firmware. This paper also sums up the effectiveness of ATM protection and the current situation of standardization in ITU-T SG13.

An ultra-broadband optical parametric amplification can be attained by a noncollinear phase-matching. The group-velocity matching of the signal and idler reduces the signal-pulse width to 14-fs in an optical parametric amplifier based on a β-BaB2O4 crystal pumped by a second harmonics of a Ti: sapphire regenerative amplifier. This simple novel method shows the potential light source of a tunable sub-10-fs pulse in a visible region.

This paper describes the design and evaluation of a high-performance multicast ATM switch and its feasibility study, including its 40 Gbit/s LSI packaging. The multicast switch is constructed using a serial combination of rerouting networks and employs an adapted Boolean interval-splitting scheme for a generalized self-routing algorithm. Analysis and computer simulation results show that the cell loss probability is easily controlled by increasing the number of switching stages. It is shown that the switch configuration can be transformed into other patterns to be built from banyan-based subnetworks of arbitrary size for LSI packaging. It is also shown that an LSI chip integrating an 88 banyan-based subnetwork using 0. 25-µm CMOS/SIMOX technology can attain a 40-Gbit/s switching capability.

The aim of this study is to offer additional experimental evaluation on learning algorithms for artificial neural networks by testing and comparing the normalized backpropagation algorithm (NBP), previously proposed by the authors, and six other alternatives based on a particular application to financial forecasting. The algorithms are the original backpropagation (OBP), the NBP, backpropagation with momentum (two versions), the delta-bar-delta, the superSAB, the rprop and the quickprop algorithm.

A 2-GHz monolithic Si-bipolar logarithmic/ limiting amplifier is described. It features a waveform-dependent current phase shifter that compensates for the intrinsic dependence of unit-amplifier phase shifts on input signal amplitudes and layout techniques that minimize crosstalk in Si substrate. The amplifier dissipates 250 mW at a 3-V supply, which is less than 1/4 of that of previously reported ICs. The dynamic range of a received signal strength indicator (RSSI) is 60 dB and the limited-output phase deviation is less than 7 deg. at 2 GHz. Therefore, this amplifier is quite suitable for single-conversion transceivers for broadband wireless access systems.

Multicast ATM switches are essential to support various types of services in the Broadband ISDN. In this paper we present an efficient architecture to support multicasting in shared buffer ATM switches. A lookahead technique is employed to resolve the head-of-line blocking problem in the multicast-queue approach, thus improving the throughput of the multicast traffic. The arbitration between multicast and unicast services is investigated to prevent the lookahead technique from increasing the multicast dominance. We show through performance and complexity comparisons that with a small hardware overhead over the multicast-queue approach, our architecture provides a throughput performance comparable to address-duplication or searchable-queue-based approaches.

In this paper, we propose a new multicast address scheme based on bit map address (BA) and vertex isolation address (VIA) schemes. The proposed scheme can be utilized by the self-routing switch in a speed manner, while preserving the multicast capability. We analyze the processing delay of the proposed scheme and show the efficiency.

Multicasting is an important feature for any switching network being intended to support broadband integrated services digital networks (B-ISDN). This paper proposes an improved multicast packet switch based on Lee's nonblocking copy network. The improved design retains the desirable features of Lee's network including its nonblocking property while adopting techniques to overcome the various limitations mentioned in various literature. The proposed network architecture utilizes d-dilated banyan networks to increase the amount of cells that can be replicated within the copy network. Cell splitting is used to optimize the utilization of the network's available bandwidth. Furthermore, the proposed architecture allows for the modular expansion in capacity to accomodate changing traffic patterns. The modular design of the proposed switch likewise offers easy handling and replacement of faulty modules.

We describe an algorithm for efficiently compositing partial images generated during parallel volume rendering on a distributed memory parallel computer. In this object space partitioning algorithm, each PE is assigned to several subvolumes where each subvolume has a corresponding local frame buffer. After volume rendering is performed independently for each subvolume, the partial images stored in the local frame buffers are combined to generate a complete image. During this compositing process, the communication of partial image data between the PEs is kept minimal by assigning PEs to subvolumes in an interleaved manner. This assignment makes possible a reduction in communication in the axis direction in which there is the most communication. Experimental results indicate that a 9% to 35% reduction in the total rendering time can be attained with no additional data structures and no memory overhead.

Mobile databases will play an important role in mobile computing environment, to provide data storing and data retrieval functionalities which are needed by most applications. In mobile computing environment, the wireless communication poses some problems, which require us to minimize its use. Replication is a database technique that is commonly used to fulfill the requirement in minimizing network usage. In this paper, we propose two replica allocation strategies, called primary-copy tracking replica allocation (PTRA) and user majority replica allocation (UMRA), which are better suited to the mobile computing environment. Their proposals are intended to cope with cost performance issues in data replication due to user mobility in mobile computing environment. To investigate their effectiveness, we provide access cost analysis and comparison on these strategies and the static replica allocation (SRA) strategy. We show that our proposed strategies outperform the SRA strategy when user mobility (inter-cell movement) is relatively low as compared with data access rate.

In this paper, we propose an algorithm of classification by feature partitioning (CFP) which learns concepts in the batch mode. The proposed algorithm achieved almost the same predictive accuracies as the best results of a CFP algorithm presented by Guvenir and Sirin. However, our algorithm is not affected by parameters and the order of examples.

This paper first investigates a relationship between inkdot-depth and inkdot-size of inkdot two-way alternating Turing machines and pushdown automata with sublogarithmic space, and shows that there exists a language accepted by a strongly loglog n space-bounded alternating pushdown automaton with inkdot-depth 1, but not accepted by any weakly o (log n) space-bounded and d (n) inkdot-size bounded alternating Turing machine, for any function d (n) such that limn [d (n)log n/n1/2] = 0. In this paper, we also show that there exists an infinite space hierarchy among two-way alternating pushdown automata with sublogarithmic space.

A processor allocation scheme for mesh computers greatly affects their system utilization. The performance of an allocation scheme is largely dependent on its ability to detect available submeshes. We propose a new type of submesh, called a link-disjoint submesh, for processor allocation in mesh computers. This type of submesh increases the submesh recognition capability of an allocation scheme. A link-disjoint submesh is not a contiguous submesh as in the previous scheme, but this submesh still has no common communication link with any other submesh. When wormhole routing or circuit switching is used, the communication delay caused by non-contiguous processor allocation is minor. Through simulation, the performance of our scheme is measured and compared to the previous schemes in terms of such parameters as finish time and system utilization. It is shown through simulation that the link-disjoint submesh increases the performance of an allocation scheme.

We have developed an efficient recursive algorithm based on the interacting multiple model (IMM) for enhancing speech degraded by additive white noise. The clean speech is modeled by the hidden filter model (HFM). The simulation results shows that the proposed method offers performance gains relative to the previous one with slightly increased complexity.

This paper extends left-incompatible term rewriting systems defined by Toyama et al. It is also shown that the functional strategy is normalizing in the class, where the functional strategy is the reduction strategy that finds index by some rule selection method and top-down and left-to-right lazy pattern matching method.

Many rewriting systems, including those of terms, strings, graphs, and conjunction of atoms, are used throughout computer science and artificial intelligence. While the concepts of "substitutions," "places" in objects and the "replacement" of "subobjects" by other objects seems to be common to all rewriting systems, there does not exist a common foundation for such systems. At the present time, many of the theories are constructed independently, one for each kind of rewritten object. In the conventional approach, abstract rewriting systems are used to discuss common properties of all rewriting systems. However, they are too abstract to capture properties relating to substructures of objects. This paper aims to provide a first step towards a unified formalization of rewriting systems. The major problem in their formulation may be the formalization of the concept of "places". This has been solved here by employment of the concept of contexts rather than by formalization of places. Places determine subobjects from objects, while, conversely, contexts determine objects from subobjects. A class of rewriting systems, called β rewriting systems, is proposed. It is defined on axiomatically formulated base structures, called β structures, which are used to formalize the concepts of "contexts" and "replacement" common to many rewritten objects. The class of β rewriting systems includes very important systems such as semi-Thue systems and Petri Nets. Abstract rewriting systems are also a subclass of β rewriting systems.

The proposed high-power-factor converter is constructed with a flyback converter, and locates the energy-storage capacitor on the secondary side of the transformer. A high power-factor can be obtained without needing to detect any current, and the ZVS operation can be achieved without auxiliary switches. To make the best use of these advantages in the converter, ZVS operations and power-factor characteristics in the converter were analyzed. From the analytical results, the effective control method for achieving ZVS was examined. Using a bread-board circuit controlled by this method, a power-factor of 0.99 and a conversion efficiency of 88% were measured.