Source coding with a helper is one of the most fundamental fixed-length source coding problem for correlated sources. For this source coding, Wyner and Ahlswede-Korner showed the achievable rate region which is the set of rate pairs of encoders such that the probability of error can be made arbitrarily small for sufficiently large block length. However, their expression of the achievable rate region consists of the sum of indefinitely many sets. Thus, their expression is not useful for computing the achievable rate region. This paper deals with correlated sources whose conditional distribution is related by a binary-input output-symmetric channel, and gives a parametric form of the achievable rate region in order to compute the region easily.

A multiuser precoding algorithm based on matching weighted signal-to-leakage-and-noise ratio (SLNR) is proposed for multiuser MIMO downlink systems. In the proposed algorithm, the matching weight factor is selected based on the effective channel gain, and the leakage power caused by each user is weighted by the factor. The precoding vector is obtained by maximizing the matching weighted SLNR. Simulation results show the superiority of the proposed scheme in terms of bit error rate over the conventional SLNR schemes.

In this paper, we propose a wireless network coding diversity technique based on hybrid amplify-and-forward/decode-and-forward relay method employing adaptive power control for two-hop wireless networks in order to improve relay node position flexibility. Wireless network coding diversity based on hybrid relay method selects either modulation symbol level wireless network coding diversity or bit sequence level wireless network coding diversity as its wireless network coding diversity scheme according to the cyclic redundancy check result at the relay node. Moreover, the adaptive power control scheme proposed here controls the relay node's transmit power according to its position. Computer simulations verify that wireless network coding diversity based on hybrid relay method employing the adaptive power control scheme can expand the area wherein the relay node can be located while satisfying the required communication quality by 4.56 times compared to the conventional wireless network coding diversity scheme. Therefore, we confirm that our proposed scheme can increase relay node position flexibility.

The Boolean network (BN) can be used to create discrete mathematical models of gene regulatory networks. In this paper, we consider three problems on BNs that are known to be NP-hard: detection of a singleton attractor, finding a control strategy that shifts a BN from a given initial state to the desired state, and control of attractors. We propose integer programming-based methods which solve these problems in a unified manner. Then, we present results of computational experiments which suggest that the proposed methods are useful for solving moderate size instances of these problems. We also show that control of attractors is -hard, which suggests that control of attractors is harder than the other two problems.

In this work, a simple doped accumulator (DACC)-assisted relay system is proposed by using bit-interleaved coded modulation with iterative decoding (BICM-ID). An extrinsic information transfer (EXIT) chart analysis shows that DACC keeps the convergence tunnel of the EXIT curves open until almost the (1, 1) point of the mutual information, which avoids the error floor. In the relay system, errors may happen in the source-relay link (intra-link), however, they are allowed in our proposed technique where the correlation knowledge between the source and the relay is exploited at the destination node. Strong codes are not needed and even the systematic source bits can be simply extracted at the relay even though the systematic part may contain some errors. Hence, the complexity of the relay can be significantly reduced, and thereby the proposed system is energy-efficient. Furthermore, the error probability of the intra-link can be estimated at the receiver by utilizing the a posteriori log-likelihood ratios (LLRs) of the two decoders, and it can be further utilized in the iterative processing. Additionally, we provide the analysis of different relay location scenarios and compare the system performances by changing the relay's location. The transmission channels in this paper are assumed to suffer from additive white Gaussian noise (AWGN) and block Rayleigh fading. The theoretical background of this technique is the Slepian-Wolf/Shannon theorem for correlated source coding. The simulation results show that the bit-error-rate (BER) performances of the proposed system are very close to theoretical limits supported by the Slepian-Wolf/Shannon theorem.

This paper investigates the dominant impact on the interference rejection combining (IRC) receiver due to the downlink reference signal (RS) based covariance matrix estimation scheme. When the transmission modes using the cell-specific RS (CRS) in LTE/LTE-Advanced are assumed, the property of the non-precoded CRS is different from that of the data signals. This difference poses two problems to the IRC receiver. First, it results in different levels of accuracy for the RS based covariance matrix estimation. Second, assuming the case where the CRS from the interfering cell collides with the desired data signals of the serving cell, the IRC receiver cannot perfectly suppress this CRS interference. The results of simulations assuming two transmitter and receiver antenna branches show that the impact of the CRS-to-CRS collision among cells is greater than that for the CRS interference on the desired data signals especially in closed-loop multiple-input multiple-output (MIMO) systems, from the viewpoint of the output signal-to-interference-plus-noise power ratio (SINR). However, the IRC receiver improves the user throughput by more than 20% compared to the conventional maximal ratio combining (MRC) receiver under the simulation assumptions made in this paper even when the CRS-to-CRS collision is assumed. Furthermore, the results verify the observations made in regard to the impact of inter-cell interference of the CRS for various average received signal-to-noise power ratio (SNR) and signal-to-interference power ratio (SIR) environments.

Software product-line engineering is the successful reuse of technology when applied to component-based software development. The main concept and structure of this technology is developing reusable core assets by applying commonality and variability, and then developing new software reusing these core assets. Recently, the emergence of service-oriented environments, called SOA, has provided flexible reuse environments by reusing pre-developed component structure as service units; this is platform-independent and can integrate into heterogeneous environments. The core asset of an SOA is the service. Therefore, we can increase the reusability of an SOA by combining it with the concept of a product-line. These days, there exists research that combines SOA and product-lines, taking into account reusability. However, current research does not consider the interaction between the provider and consumer in SOA environments. Furthermore, this research tends to focus on more fragmentary aspects of product-line engineering, such as modeling and proposing variability in services. In this paper, we propose a mechanism named 2-Level SOA, including a supporting environment. This proposed mechanism deploys and manages the reusable service. In addition, by reusing and customizing this reusable service, we can develop and generate new services. Our proposed approach provides a structure to maximize the flexibility of SOA, develops services that consider systematic reuse, and constructs service-oriented applications by reusing this pre-developed reusable service. Therefore, our approach can increase both efficiency and productivity when developing service-oriented applications.

In this paper, we propose a virtualization architecture for a multi-core embedded system to provide more system reliability and security while maintaining performance and without introducing additional special hardware supports or implementing a complex protection mechanism in the virtualization layer. Embedded systems, especially consumer electronics, have often used virtualization. Virtualization is not a new technique, as there are various uses for both GPOS (General Purpose Operating System) and RTOS (Real Time Operating System). The surge of the multi-core platforms in embedded systems also helps consolidate the virtualization system for better performance and lower power consumption. Embedded virtualization design usually uses two approaches. The first is to use the traditional VMM, but it is too complicated for use in the embedded environment without additional special hardware support. The other approach uses the microkernel, which imposes a modular design. The guest systems, however, would suffer from considerable modifications in this approach, as the microkernel allows guest systems to run in the user space. For some RTOSes and their applications originally running in the kernel space, this second approach is more difficult to use because those codes use many privileged instructions. To achieve better reliability and keep the virtualization layer design lightweight, this work uses a common hardware component adopted in multi-core embedded processors. In most embedded platforms, vendors provide additional on-chip local memory for each physical core, and these local memory areas are only private to their cores. By taking advantage of this memory architecture, we can mitigate the above-mentioned problems at once. We choose to re-map the virtualization layer's program on the local memory, called SPUMONE, which runs all guest systems in the kernel space. Doing so, it can provide additional reliability and security for the entire system because the SPUMONE design in a multi-core platform has each instance installed on a separate processor core. This design differs from traditional virtualization layer design, and the content of each SPUMONE is inaccessible to the others. We also achieve this goal without adding overhead to the overall performance.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, most previous studies are mainly focused on the bipolar transistor circuits and no paper presents the global convergence theorems of homotopy methods for MOS transistor circuits. Moreover, due to the improvements and advantages of MOS transistor technologies, extending the homotopy methods to MOS transistor circuits becomes more and more necessary and important. This paper proposes two nonlinear homotopy methods for MOS transistor circuits and proves the global convergence theorems for the proposed MOS nonlinear homotopy method II. Numerical examples show that both of the two proposed homotopy methods for MOS transistor circuits are more effective for finding DC operating points than the conventional MOS homotopy method and they are also capable of finding DC operating points for large-scale circuits.

This paper introduces new FPGA design of user-monitoring system for power management of PC display. From the camera readings the system detects whether the user looks at the screen or not and produces signals to control the display backlight. The system provides over 88% eye detection accuracy at 8f/s image processing rate. We describe new eye-tracking algorithm and hardware and present the results of its experimental evaluation in prototype display power management system.

A concurrent FIFO queue is a widely used fundamental data structure for parallelizing software. In this letter, we introduce a novel concurrent FIFO queue algorithm for multicore architecture. We achieve better scalability by reducing contention among concurrent threads, and improve performance by optimizing cache-line usage. Experimental results on a server with eight cores show that our algorithm outperforms state-of-the-art algorithms by a factor of two.

L-band SiGe HBT frequency-tunable differential amplifiers with dual-bandpass or dual-bandstop responses have been developed for the next generation adaptive and/or reconfigurable wireless radios. Varactor-loaded dual-band resonators comprised of series and parallel LC circuits are employed in the output circuit of differential amplifiers for realizing dual-bandpass responses as well as the series feedback circuit for dual-bandstop responses. The varactor-loaded series and parallel LC resonator can provide a wider frequency separation between dual-band frequencies than the stacked LC resonator. With the use of the varactor-loaded dual-band resonator in the design of the low-noise SiGe HBT differential amplifier with dual-bandpass responses, the lower-band frequency can be varied from 0.58 to 0.77 GHz with a fixed upper-band frequency of 1.54 GHz. Meanwhile, the upper-band frequency can be varied from 1.1 to 1.5 GHz for a fixed lower-band frequency of 0.57 GHz. The dual-band gain was 6.4 to 13.3 dB over the whole frequency band. In addition, with the use of the varactor-loaded dual-band resonator in the design of the low-noise differential amplifier with dual-bandstop responses, the lower bandstop frequency can be varied from 0.38 to 0.68 GHz with an upper bandstop frequency from 1.05 to 1.12 GHz. Meanwhile, the upper bandstop frequency can be varied from 0.69 to 1.02 GHz for a lower bandstop frequency of 0.38 GHz. The maximal dual-band rejection of gain was 14.4 dB. The varactor-loaded dual-band resonator presented in this paper is expected to greatly contribute to realizing the next generation adaptive and/or reconfigurable wireless transceivers.

This paper proposes a high frequency resolution Digitally-Controlled Oscillator (DCO) using a single-period control bit switching scheme. The proposed scheme controls the tuning word of DCO in a single period for the fine frequency tuning. The LC type DCO is implemented to realize the proposed scheme, and is fabricated using a standard 65 nm CMOS technology. The measurement results show that the implemented DCO improves the frequency resolution from 560 kHz to 180 kHz without phase noise degradation with an additional area of 200 µm2.

This paper presents a blocked united algorithm for the all-pairs shortest paths (APSP) problem. This algorithm simultaneously computes both the shortest-path distance matrix and the shortest-path construction matrix for a graph. It is designed for a high-speed APSP solution on hybrid CPU-GPU systems. In our implementation, two most compute intensive parts of the algorithm are performed on the GPU. The first part is to solve the APSP sub-problem for a block of sub-matrices, and the other part is a matrix-matrix “multiplication” for the APSP problem. Moreover, the amount of data communication between CPU (host) memory and GPU memory is reduced by reusing blocks once sent to the GPU. When a problem size (the number of vertices in a graph) is large enough compared to a block size, our implementation of the blocked algorithm requires CPU GPU exchanging of three blocks during a block computation on the GPU. We measured the performance of the algorithm implementation on two different CPU-GPU systems. A system containing an Intel Sandy Bridge CPU (Core i7 2600K) and an AMD Cayman GPU (Radeon HD 6970) achieves the performance up to 1.1 TFlop/s in a single precision.

Reconfigurable computing system is a class of parallel architecture with the ability of computing in hardware to increase performance, while remaining much of flexibility of a software solution. This architecture is particularly suitable for running regular and compute-intensive tasks, nevertheless, most compute-intensive tasks spend most of their running time in nested loops. Polyhedron model is a powerful tool to give a reasonable transformation on such nested loops. In this paper, a number of issues are addressed towards the goal of optimization of affine loop nests for reconfigurable cell array (RCA), such as approach to make the most use of processing elements (PE) while minimizing the communication volume by loop transformation in polyhedron model, determination of tilling form by the intra-statement dependence analysis and determination of tilling size by the tilling form and the RCA size. Experimental results on a number of kernels demonstrate the effectiveness of the mapping optimization approaches developed. Compared with DFG-based optimization approach, the execution performances of 1-d jacobi and matrix multiplication are improved by 28% and 48.47%. Lastly, the run-time complexity is acceptable for the practical cases.

A novel and compact electro-optic modulator implemented by a combination of a 12 multimode interference (MMI) coupler and an integrated Mach-Zehnder interferometer (MZI) modulator consisting of a microring and a phase modulator (PM) is presented and analyzed theoretically. It is shown that the proposed modulator offers both ultra-linearity and high output RF gain simultaneously, with no requirements for complicated and precise direct current (DC) control.

A fractional-N phase-locked loop (PLL) is designed for the DigRF interface. The digital part of the PLL mainly consists of a dual-mode phase frequency detector (PFD), a digital counter, and a digital delta-sigma modulator (DSM). The PFD can operate on either 52 MHz or 26 MHz reference frequencies, depending on its use of only the rising edge or both the rising and the falling edges of the reference clock. The interface between the counter and the DSM is designed to give enough timing margin in terms of the signal round-trip delay. The circuitry is implemented using a 90-nm CMOS process technology with a 1.2-V supply, draining 1 mA.

This letter presents a flexible signal structure supporting localization service for time domain synchronous OFDM (TDS-OFDM) in multi-service transmission applications. Localization is treated as one specific service and the corresponding data is allocated within the physical layer pipe (PLP) of the first subframe. The concept of variable sub-carrier spacing to combat Doppler spread is also introduced for the localization service. Simulation results indicate that the proposed scheme outperforms the conventional scheme and at the same time achieves high positioning accuracy.

Turbo codes and LDPC (Low-Density Parity-Check) codes are two of the most powerful error correction codes that can approach Shannon limit in many communication systems. But there are little architecture presented to support both LDPC and Turbo codes, especially by the means of ASIC. This paper have implemented a common architecture that can decode LDPC and Turbo codes, and it is capable of supporting the WiMAX, WiFi, 3GPP-LTE standard on the same hardware. In this paper, we will carefully describe how to share memory and logic devices in different operation mode. The chip is design in a 130 nm CMOS technology, and the maximum clock frequency can reach up to 160 MHz. The maximum throughput is about 104 Mbps@5.5 iteration for Turbo codes and 136 Mbps@10iteration for LDPC codes. Comparing to other existing structure, the design speed, area have significant advantage.

This paper presents joint maximum likelihood detection (MLD) using channel coding information for orthogonal code division multiple access (CDMA) to decrease the required average received signal-to-noise power ratio (SNR) satisfying the target block error rate (BLER), and investigates the effect of joint MLD from the conventional coherent detection associated with channel coding. In the paper, we assume the physical uplink control channel (PUCCH) as specified in Release 8 Long-Term Evolution (LTE) by the 3rd Generation Partnership Project (3GPP) as the radio interface for the uplink control channel. First, we clarify the best scheme for combining correlation signals in two frequency-hopped slots and in two receiver diversity branches for joint MLD. Then, we show that the joint MLD without channel estimation, in which correlation signals are combined in squared form, decreases the required average received SNR compared to that for joint MLD with coherent combining of the correlation signals using channel estimation. Second, we show the effectiveness of joint MLD in terms of the decrease in the required average received SNR compared to the conventional coherent detection in various delay spread channels. Third, we present a comparison of the average BLER performance levels between cyclic shift (CS)-CDMA and block spread (BS)-CDMA using joint MLD. We show that when using joint MLD, BS-CDMA is superior to CS-CDMA due to a lower required received SNR in short delay spread environments and that in contrast, CS-CDMA provides a lower required received SNR compared to BS-CDMA in long delay spread environments.