In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.

A method is proposed for realizing any k-valued n-variable function with a celluler array, which consists of linear arrays (called input arrays) and a rectangular array (called control array). In this method, a k-valued n-variable function is divided into kn-1 one-variable functions and remaining (n1)-variable function. The parts of one-variable functions are realized by the input arrays, remaintng the (n1)-variable function is realized by the control array. The array realizing the function is composed by connecting the input arrays with the control array. Then, this array requires (kn2)kn-1 cells and the number is smaller than the other rectangular arrays. Next, a ternary cell circuit and a literal circuit are actually constructed with CMOS transistors and NMOS pass transistors. The experiment shows that these circuits perform the expected operations.

A fail-safe logic operation refers to such a processing operation that the output assumes the logical value zero when the operation circuit fails. The fail-safe multiple-valued logic operation is proposed as one method of logic operation. Section 2 defines the fail-asfe multiple-valued logic operation and presents an example of method for accomplishing the fail-safe multiple-valued logic operation. Section 3 describes the method of designing a fail-safe threshold operation device (window comparator) as basic device in the fail-safe multiple-valued logic operation in consideration of LSI implementation and shows an example of prototype fail-safe window comparator. This operation device has higher and lower thresholds. It oscillates and produces an operational output signal only when the input signal level falls between the higher and lower thresholds. Unless the fail-safe window comparator is supplied with input signals of higher voltage than the power supply voltage, it dose not form a feedbadk loop as required for it to oscillate. This characteristic prevents the device from erroneously producing an output signal when any failure occurs in the amplifiers comprising the oscillation circuit. The window comparator can be built as a fail-safe threshold operation device. The fail-safe characteristic is utilized in its LSI implementation. Section 4 verifies the fail-safe property of the prortotype fail-safe window comparator. It is shown that even when the LSI develops failures not evident from outsid (latent failures), it does not lose the operational function and maintains the fail-safe characteristic.

We have developed a new functional MOS transistor called Neuron MOSFET (abbreviated as neuMOS or νMOS) which simulates the function of biological neurons. The new transistor is capable of executing a weighted sum calculation of multiple input signals and threshold operation based on the result of weighted summation, all in the voltage mode at a single transistor level. By utilizing its neuron-like very powerful functional capability, various circuits essential for multiple-valued logic operation have been designed using quite simple circuit configurations. The circuit designs for data conversion between the multivalued and binary logic systems and for generating universal literal functions are described and their experimental verifications are presented. One of the most important features of νMOS multivalued lagic circuit is that the circuit operates basically in the voltage mode, thus greatly reducing the power dissipation as compared to the conventional current mode circuitry. This is indeed most essential in implementing multivalued logic systems in ultra large scale integration. Another important feature of νMOS design is in its flexibility of implementing logic functions. The functional form of a universal literal function, for instance, can be arbitrarily altered by external signals without any modifications in its hardware configuration. A circuit representing multiple-valued multithreshold functions is also proposed.

The Memory-Based Reasoning (MBR) is one of the mainstay approaches in massively parallel artificial intelligence research. However, it has not been explored from the viewpoint of hardware implementation. This paper demonstrates high robustness of the MBR, which is suitable for hardware implementation using Wafer Scale Integration (WSI) technology, and proposes a design of WSI-MBR hardware. The robustness is evaluated by a newly developed WSI-MBR simulator in the English pronunciation reasoning task, generally known as MBRTalk. The results show that defects or other fluctuations of device parameters have only minor impacts on the performances of the WSI-MBR. Moreover, it is found that in order to get higher reasoning accuracy, the size of the MBR database is much more crucial than the computation resolution. These features are proved to be caused by the fact that MBR does not rely upon each single data unit but upon a bulk data set. Robustness in the other MBR tasks can be evaluated in the same manner as discussed in this paper. The proposed WSI-MBR processor takes advantage of benefits discovered in the simulation results. The most area-demanding circuits--that is, multipliers and adders--are designed by analog circuits. It is expected that the 1.7 million processors will be integrated onto the 8-inch silicon wafer by the 0.3 µm SRAM technology.

This paper discusses a formulation of a basic theory of the information systems, where information is not only transmitted, but is also processed and memorized during the transmission. A deterministic procedure applied by an information system is defined as a logical work, and two measurements with information X, information quantity I(X) and information vitality T(X), are introduced. A system with the ability of transmitting, processing and memorizing information is called an information engine. A system of interconnected information engines is called an information network. The power of an information engine is defined as the maximum capacity of the logical works performed by the engine, and important properties of total power of information network are derived. Response time characteristics and cost minimizing problems of an information network are also discussed.

This paper describes a text-independent speaker recognition method using predictive neural networks. For text-independent speaker recognition, an ergodic model which allows transitions to any other state, including selftransitions, is adopted as the speaker model and one predictive neural network is assigned to each state. The proposed method was compared to quantization distortion based methods, HMM based methods, and a discriminative neural network based method through text-independent speaker identification experiments on 24 female speakers. The proposed method gave the highest identification rate of 100.0%, and the effectiveness of predictive neural networks for representing speaker individuality was clarified.

This paper discusses multiple-valued memory circuit using floating gate devices. It is an object of the paper to provide a new and improved analog memory device, which permits the memory of an amount of charges that accurately corresponds to analog information to be stored.

Some problems in formal language theory are considered and are shown to be deterministic exponential time complete. They include the problems for a given context-free grammar G, a nondeterministic finite automaton M, a deterministic pushdown automaton MD, of determining whether L(G)L(M), and whether L(MD)L(M). Polynomial time reductions are presented from the pebble game problem, known to be deterministic exponential time complete, to each of these problems.

In this paper, a methodology for designing the architecture of the processor array for wide class of image processing algorithms is proposed. A concept of spatially expanding the SFG description which enables us to handle the problem as merely one-dimensional signal processing is used in constructing the methodology. Problem of I/O interface which is critical in real-time processing is also considered.

An adaptive algorithm is presented for fuzzy clustering of data. Partitioning is fuzzified by addition of an entropy term to objective functions. The proposed method produces more convex membership functions than those given by the fuzzy c-means algorithm.

This paper reviews the application of optical technologies to phased array antennas. The performance of the fibre transmission medium and of sources and detectors is reviewed, leading to simple expressions for transmission loss and noise performance. Both coherent and non-coherent beam forming techniques are considered. Future trends, including the use of optical amplifiers and coherent signal generation, will also be discussed.

The problem of two-dimensional scattering of electromagnetic waves by a grating with several strips arbitrarily oriented in one period is analyzed by means of the Wiener-Hopf technique together with the formulation using the concept of the mutual field. A formulation for the analysis of multiple scattering from the grating is based on the representation of the scattered field by a grating composed of one strip in one period. The Wiener-Hopf equations and a representation of the scattered wave are obtained. The characteristic of the sampling function is used to expand the unknown function associated with the field on the strip into a series, and then the Wiener-Hopf equations are reduced to a set of simultaneous equations. For evaluation of the convergence and the errors in the numerical results, the relative error with respect to the extrapolated value and the square error for satisfaction of the boundary condition are computed. From numerical comparison of the present method with other various methods, it is found that the present method provides us accurate results. Some numerical examples of the reflection coefficients are presented for the reflection grating and transmission gratings.

Compared to multi-level signature file techniques, PSF (Partitioned Signature File) technique has less processing overhead by its characteristics of a simple file organization. In a multi-processor environment, the PSF technique also has an advantage that queries can be processed in parallel effectively by allocating one or more partitions to each processor. Main point of the PSF technique is a partitioning scheme based on a key selection. In this paper, an n-BFK (n-Bounded Floating Key) partitioning scheme is proposed, in which the number of segments for a key selection is bounded by n. The cost model is developed for the performance evaluation of the proposed scheme. By performance comparison with the existing schemes, the efficiencies of the proposed scheme are shown with respect to a disk access cost, a signature reduction ratio, and an uniformity of workload.

A shielded velocity-matched Ti:LiNbO3 optical modulator with a ridge is investigated. The analytical method is based on the second-order triangular element finite element method. The thickness of the coplanar waveguide traveling-wave electrode is taken into consideration and the relationship between the electrode thickness and optimum overlaid layer thickness is clarified. Incorporating a ridge into these Ti:LiNbO3 optical modulators can improve not only their modulation bandwidth but also their driving voltage.

The performance of a traveling wave Mach-Zehnder external optical modulator (EOM) mixer is described and compared with a conventional diode mixer's performance. Additionally, by incorporating external circuitry, the EOM mixer can provide single sideband suppression in addition to the inherent local oscillator suppression. The basic frequency mixing function of the EOM mixer is first described theoretically and then extended to the sideband suppression case. The performance of both configurations is also presented. Achievable electrical isolation between LO (carrier) and RF (upconverted data signal at LOIF) frequencies is greater than 95 dB and total link conversion loss is 37 dB in this demonstration with a laser diode source. Sideband suppression of greater than 43 dB with respect to the desired sideband at the photodetector output is achieved.

This letter discusses a microstrip line with an open-end termination in which the reflected microwaves can be optically controlled by a laser illumination. The frequency characteristics are emphasized rather than the time domain ones. The reflection characteristics have been demonstrated experimentally and theoretically for the frequency range of 24 GHz. In the theoretical treatment both the conductance and the capacitance are considered in the equivalent circuit model of the open end of the strip.

This paper theoretically evaluates the external electro-optic (EO) sampling of high-speed electrical signals using poled polymers as materials for a proximity electric-field sensor. Based on the derivation of the half-wave voltage and the analysis of a static electric field coupled to the polymeric media placed over IC interconnections, invasiveness, voltage sensitivity, and spatial resolution have been discussed. The polymeric sensors have shown to be used in contact with the IC interconnections with negligibly small invasiveness, thus making polymeric sensors provide higher sensitivity and spatial resolution than inorganic crystals such as GaAs and KD*P.

In coherent optical subcarrier multiplexing (SCM) systems, the performance degradation of the system due to the phase noise of lasers restricts the maximum number of stations and channels that the system can serve. However, the effects of phase noise on the performance of the coherent SCM system with distributing Local Oscillator (LO) in local loop have not been analyzed. On the other hand, a limit on both the number of channels and stations can be effectively alleviated by using coding technique. In this paper, the effects of phase noise of lasers on the performance of frequency shift keying (FSK) SCM system with distributing LO in local loop are analyzed in terms of carrier-to-noise ratio (CNR) penalty. Second, the effects of Reed-Solomon (RS) coding on FSK SCM system with distributing LO in local loop are analyzed. It is shown that both the number of channels and stations can be increased by using coding technique.

This paper discusses the conversion of spatial resolution (pixel density) and amplitude resolution (levels of brightness) for multilevel images. A source image is sampled by an image scanner or a video camera, and a converted image is printed by a printer with the capability of higher spatial but lower amplitude resolution than the image input device. In the proposed method, the impulse response of the scanner sensor is modeled to obtain pixel values from the convolution of the impulse and the image signal. Discontinuous areas (edge) of the original image are detected locally according to the impulse model and neighbouring pixel values. The edge route is estimated which gives the pixel values for the output resolutions. Comparison of the proposed method with two conventional methods, reciprocal distance weight interpolation and pixel replication, shows higher edge quality for the proposed method.