We observed a ship as a radar target embedded in sea clutter using a millimeter wave radar. The shape of the ship and sea clutter were discriminated by using texture analysis in image processing. As a discriminator, a nonlinear transformation of a local pattern was defined to deal with high order statistics.

This paper proposes new architecture LSIs based on wave-parallel computing to provide an essential solution to the interconnection problems in massively parallel processing. The basic concept is ferquency multiplexing of digital information, which enables us to utilize the parallelism of electrical (or optical) waves for parallel processing. This wave-parallel computing concept is capable of performing several independent binary funtions in parallel with a single module. In this paper, we discuss the design of wave-parallel image processing LSI to demonstrate the feasibility of reducing the number of interconnections among modules.

Toward the age of ultra-high-density digital ULSI systems, the development of new integrated circuits suitable for an ultimately fine geometry feature size will be an important issue. Resonant-tunneling (RT) diodes and transistors based on quantum effects in deep submicron geometry are such kinds of key devices in the next-generation ULSI systems. From this point of view, there has been considerable interests in RT diodes and transistors as functional devices for circuit applications. Especially, it has been recognized that RT functional devices with multiple peaks in the current-voltage (I-V) characteristic are inherently suitable for implementing multiple-valued circuits such as a multiple-state memory cell. However, very few types of the other multiple-valued logic circuits have been reported so far using RT devices. In this paper, a new multiple-valued programmable logic array (MVPLA) based on RT devices is proposed for the next-generation ULSI-oriented hardware implementation. The proposed MVPLA consists of 3 basic building blocks: a universal literal circuit, an AND circuit and a linear summation circuit. The universal literal circuit can be directly designed by the combination of the RT diodes with one peak in the I-V characteristic, which is programmable by adjusting the width of quantum well in each RT device. The other basic building blocks can be also designed easily using the wired logic or current-mode wired summation. As a result, a highdensity RT-diode-based MVPLA superior to the corresponding binary implementation can be realized. The device-model-based design method proposed in this paper is discussed using static characteristics of typical RT diode models.

Three dimensional (3-D) optics offers potential advantages to the massively-parallel systems over electronics from the view point of information transfer. The purpose of this paper is to survey some aspects of the 3-D optical interconnection technology for the future massively-parallel computing systems. At first, the state-of-art of the current optoelectronic array devices to build the interconnection networks are described, with emphasis on those based on the semiconductor technology. Next, the principles, basic architectures, several examples of the 3-D optical interconnection systems in neural networks and multiprocessor systems are described. Finally, the issues that are needed to be solved for putting such technology into practical use are summarized.

Superscalar processors improve performance by exploiting instruction-level parallelism (ILP). ILP in a basic block is, however, not sufficient on non-numerical applications for gaining substantial speedup. Instructions across branches are required to be executed in parallel to dramatically improve performance. That is, speculative execution is strongly required. Boosting is a general solution to achieving speculative execution. Boosting labels an instruction to be speculatively executed, and the hardware handles side-effects. This paper describes the efficient implementation of boosting in terms of cost/performance trade-offs. Our policy in implementation is beneficial in code scheduling heuristics, penalties imposed by code duplication to maintain program semantics, and area cost. This paper also describes a branch scheme which minimizes branch penalty. Branch delay causes crucial penalties on the performance of superscalar processors since multiple delay slots exist even in a single delay cycle. Our scheme is the fetching of both sequential and target instructions, and either of them is selected on a branch. No delay cycle can be imposed. This scheme is realized by a combination of static code movement and hardware support. As a result, we reduce branch penalty with small cost. Simulation results show that our ideas are highly effective in improving the performance of a superscalar processor.

To realize next-generation high performance ULSI processors, it is a very important issue to reduce the critical delay path which is determined by a cascade chain of basic gates. To design highly parallel digital operation circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the non-linear digital system. On the other hand, the use of the linear concept in the digital system seems to be very attractive because analytical methods can be utilized. To meet the requirement, we propose a new design method of highly parallel linear digital circuits for unary operations using the concept of a cycle and a tree. In the linear digital circuit design, the analytical method can be developed using a representation matrix, so that the search procedure for optimal locally computable circuits becomes very simple. The evaluations demonstrate the usefulness of the circuit design algorithm.

A method to analyze two-pattern test capabilities of autonomous test pattern generator (TPG) circuits for use in built-in self-testing are described. The TPG circuits considered here include arbitrary autonomous linear sequential circuits in which outputs are directly fed out from delay elements. Based on the transition matrix of a circuit, it is shown that the number of distinct transitions in a subspace of state variables can be obtained from rank of the submatrix. The two-pattern test capabilities of LFSRs, cellular automata, and their fast parallel implementation are investigated using the transition coverage as a metric. The relationships with dual circuits and reciprocal circuits are also mentioned.

This letter presents a new algorithm for echo cancellers, which prevents the reduction of echo return loss due to a double-talk. The essence of the algorithm is to introduce signal delays to avoid the reduction. A convergence condition in the algorithm was examined by using the IIR filter expression of the NLMS algorithm, and it was concluded that the IIR filter should be a low pass filter with unity gain. The condition is accomplished by selecting a small step gain.

A radial line slot antenna (RLSA) is a high gain and high efficiency planar array. A single-layered RLSA is much simple in structure but the slot length must be varied to synthesize uniform aperture illumination. These are now commercialized for 12GHz band DBS reception. In RLSAs, considerable power is dissipated in the termination as is common to other traveling wave antennas; the uniform aperture illumination is not the optimum condition for high gain in RLSAs. Authors proposed a theoretical method reducing the termination loss for further efficiency enhancement. This paper presents the measured performances of the SL-RLSAs of this design with non-uniform aperture illumination. The efficiency enhancement of about 10% is observed; the measured gain of 36.7dBi (87%) and 32.9dBi (81%) for a 0.6mφ and 0.4mφ antennas respectively verify this technique.

Sea clutter was measured using an X-band radar at very high grazing angles between 8.2 and 17.5. The sea state was 7 with the wave height of 6 to 9m. The wind velocity was 25m/s. It is shown that sea clutter amplitudes obey the log-normal and K distributions using the Akaike Information Criterion (AIC) , which is more rigorous fit to the distribution to the data than the least squares method.

We propose a new architecture of Functional Memory type Parallel Processor (FMPP) architectures called bit-parallel block-parallel (BPBP) FMPP. Design details of a prototype BPBP FMPP chip are also shown. FMPP is a massively parallel processor architecture that has a memory-based simple two-dimensional regular array structure suitable for memory VLSI technology. Computation space increases as integration density of memory increases. Computation time does not depend on the number of processors. So far, a bit-serial word-parallel (BSWP) implementation based on a content addressable memory (CAM) is mainly investigated as one of promising architectures of FMPP. In a BSWP FMPP, each word of a CAM works as a processor, and the amount of hardware is minimized by abopting a bit-serial operation, thus maximizing integration scale. The BSWP FMPP, however, does not allow operations between two words, which restriction limits the applicability of the BSWP FMPP. On the other hand, the proposed BPBP FMPP is designed to execute logical and arithmetic operations on two words. These operations are performed simultaneously on every group of words called a block. BPBP FMPP hereby achieves a high performance while maintaining high integration density of the BSWP, and is suitable for various applications.

This system called COKIS automatically extracts knowledge about C functions from the UNIX on-line manual by using its description paragraph and the user can interactively inquire to the system in order to know about UNIX C functions. The idea is motivated on the one side to free users from being involved in an exhaustive knowledge acquisition in the past, and to examine problems in understanding knowledge itself on the other. We propose Memory Processor which is implemented to realize extracting knowledges from corpus and processing dialogues in the inquiry system at the same modules.

Since semiconductor memory chip has been growing rapidly in its capacity, memory testing has become a crucial problem in RAMs. This paper proposes a new RAM test algorithm, called generalized marching test (GMT), which detects static and dynamic pattern sensitive faults (PSF) in RAM chips. The memory array with N cells is partitioned into B sets in which every two cells has a cell-distance of at least d. The proposed GMT performs the ordinary marching test in each set and finally detects PSF having cell-distance d. By changing the number of partitions B, the GMT includes the ordinary marching test for B1 and the walking test for BN. This paper demonstrates the practical GMT with B2, capable of detecting PSF, as well as other faults, such as cell stuck-at faults, coupling faults, and decoder faults with a short testing time.

A new neural network system for object recognition is proposed which is invariant to translation, scaling and rotation. The system consists of two parts. The first is a preprocessor which obtains projection from the input image plane such that the projection features are translation and scale invariant, and then adopts the Rapid Transform which makes the transformed outputs rotation invariant. The second part is a neural net classifier which receives the outputs of preprocessing part as the input signals. The most attractive feature of this system is that, by using only a simple shift invariant transformation (Rapid transformation) in conjunction with the projection of the input image plane, invariancy is achieved and the system is of reasonably small size. Experiments with six geometrical objects with different degrees of scaling and rotation shows that the proposed system performs excellent when the neural net classifier is trained by the Cascade-correlation learning algorithm proposed by Fahlman and Lebiere.

We propose a method of diagnosing any logical fault in combinational circuits through a repetition of the single fault-net location procedure with the aid of probing, called SIFLAP-G. The basic idea of the method has been obtained through an observation that a single error generated on a fault-net often propagates to primary outputs under an individual test even though multiple fault-nets exist in the circuit under test. Therefore, candidates for each fault-net are first deduced by the erroneous path tracing under the single fault-net assumption and then the fault-net is found out of those candidates by probing. Probing internal nets is done only for some of the candidates, so that it is possible to greatly decrease the number of nets to be probed. Experimental results show that the number seems nearly proportional to the number of fault-nets (about 35 internal nets per fault-net), but almost independent of the type of faults and the circuit size.

A strictly nonblocking 88 matrix switch was designed and fabricated using silica-based planar lightwave circuits (PLC) on a silicon substrate. The average insertion loss was 11 dB in the TE mode and 11.3 dB in the TM mode. The average switch element extinction ratio was 16.7 dB in the TE mode and 17.7 dB in the TM mode. The accumulated crosstalk was estimated to be 7.4 dB in the TE mode and 7.6 dB in the TM mode. The driving power of the phase shifter required for switching was about 0.5 W and the polarization dependence of the switching power was 4%. The switching response time was 1.3 msec. The wavelength range with a switch extinction ratio of over 15 dB was 1.31 µm30 nm.

We have developed a digital coprocessor with a dynamically reconfigurable pipeline architecture specified for a layered neural network which executes on-chip learning. The coprocessor attains a learning speed of 18 MCUPS that is approximately twenty times that of the conventional DSP. This coprocessor obtains expansibility in the calculation through a larger multi-layer, network by means of a network decomposition and a distributed processing approach.

We discuss possible new principles of information processing by utilizing microscopic, semi-microscopic and macroscopic phenomena occuring in nature. We first discuss quantum mechanical universal information processing in microscopic world governed by quantum mechanics, and then we discuss superconducting phenomena in a mesoscopic system, especially an information processing system using flux quantum. Finally, we discuss macroscopic self-organizing phenomena in biology and suggest possibility of self-organizing devices.

We propose a fully digital architecture for Kohonen network suitable for VLSI implementation. The proposed architecture adopts a functional memory type parallel processor (FMPP) architecture which has a structure similar to a content addressable memory (CAM). One word of CAM is regarded as a processing element and a group of elements forms a neuron. All processing elements execute the same operation in bit-serial but in processor-parallel. Thus the number of instructions for realizing the network algorithm is independent of the number of neurons in the network. With reference to a previously reported CAM, we estimate a network with 96 neurons for speech recognition could be integrated on three chips using a 1.2 µm process, and it operates 50 times faster than a sequential hardware. Owing to its highly regular structure of memories, the proposed hardware architecture is well compatible with current VLSI technology.

This paper presents a new redundant fault identification algorithm, REDUCT. This algorithm handles the redundant fault identification problem by transforming a given circuit into another circuit. It also reduces the complexity of the transformed circuit, which is caused by a large number of reconvergences and head lines, using five circuit reduction techniques. Further, it proves redundancies and generates test patterns for hard faults more efficiently than conventional test pattern generation algorithms. We obtained 100% fault coverage for all ISCAS85 benchmark circuits using REDUCT following the execution of the test pattern generation algorithm N2-V.