In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.

Low-sensitivity digital filters are required for accurate signal processing. Among many low-sensitivity digital filters, a method using complex allpass circuits is well-known. In this paper, a new synthesis of complex allpass circuits is proposed. The proposed synthesis can be realized more easily either only in the z-domain or in the s-domain than conventional methods. The key concept for the synthesis is based on the factorization of lossless scattering matrices. Complex allpass circuits are interpreted as lossless digital two-port circuits, whose scattering matrices are factored. Furthermore, in the cases of Butterworth, Chebyshev and inverse Chebyshev responses, the explicit formulae for multiplier coefficients are derived, which enable us to synthesize the objective circuits directly from the specifications in the s-domain. Finally design examples verify the effectiveness of the proposed method.

This paper presents a VLSI-oriented arithmetic design method using a radix-2 redundant number representation with digit set {0, 1, 2} and multiple-valued current-mode (MVCM) circuit technology. We propose a carry-propagation-free (CPF) parallel addition method with redundant digit set {0, 1, 2} which is suitable for the design with MVCM circuits. Several types of CPF parallel adders are compared and the proposed CPF parallel adder with MVCM circuits offers the best total performance with respect to speed, complexity, and power dissipation. The designed basic arithmetic circuits has sufficient noise immunity to the supply voltage fluctuation which is important for stable operations of the VLSI circuits. The CPF parallel adder is effectively used as the reduction scheme of partial products in a high-speed compact multiplier. For example, the designed 3232 bit multiplier reduces the number of active elements to two-third and the number of interconnections to one-fifth of the corresponding binary Wallace tree multiplier, where the speed is almost the same. The structure is simple and regular. The static power dissipation of the designed 32-bit multiplier is estimated to be the mean value of 212 mW and the worst case of 708 mW. The total power including dynamic power dissipation would not be so large compared with that of the 32-bit binary CMOS multiplier reported under 10 MHz operation.

This article analyzes the property of the fully interconnected neural networks as a method of solving combinatorial optimization problems in general. In particular, in order to escape local minimums in this model, we analyze theoretically the relation between the diagonal elements of the connection matrix and the stability of the networks. It is shown that the position of the global minimum point of the energy function on the hyper sphere in n dimensional space is given by the eigen vector corresponding the maximum eigen value of the connection matrix. Then it is shown that the diagonal elements of the connection matrix can be improved without loss of generality. The equilibrium points of the improved networks are classified according to their properties, and their stability is investigated. In order to show that the change of the diagonal elements improves the potential for the global minimum search, computer simulations are carried out by using the theoretical values. In according to the simulation result on 10 neurons, the success rate to get the optimum solution is 97.5%. The result shows that the improvement of the diagonal elements has potential for minimum search.

In this paper, two models for associative memory based on a measure of manhattan length are proposed. First, we propose the two-layered model which has an advantage to its implementation by using PDN. We also refer to the way to improve the recalling ability of this model against noisy input patterns. Secondly, we propose the other model which always recalls the nearest memory pattern in a measure of manhattan length by lateral inhibition. Even if a noise of input pattern is so large that the first model can not recall, this model can recall correctly against such a noisy pattern. We also confirm the performance of the two models by computer simulations.

Rapid advances in integrated circuit technology based on binary logic have made possible the fabrication of digital circuits or digital VLSI systems with not only a very large number of devices on a single chip or wafer, but also high-speed processing capability. However, the advance of processing speeds and improvement in cost/performance ratio based on conventional binary logic will not always continue unabated in submicron geometry. Submicron integrated circuits can handle multiple-valued signals at high speed rather than binary signals, especially at data communication level because of the reduced interconnections. The use of nonbinary logic or discrete-analog signal processing will not be out of the question if the multiple-valued hardware algorithms are developed for fast parallel operations. Moreover, in VLSI or ULSI processors the delay time due to global communications between functional modules or chips instead of each functional module itself is the most important factors to determine the total performance. Locally computable hardware implementation and new parallel hardware algorithms natural to multiple-valued data representation and circuit technologies are the key properties to develop VLSI processors in submicron geometry. As a result, multiple-valued VLSI processors make it possible to improve the effective chip density together with the processing speed significantly. In this paper, we summarize several potential advantages of multiple-valued VLSI processors in submicron geometry due to great reduction of interconnection and due to the suitability to locally computable hardware implementation, and demonstrate that some examples of special-purpose multiple-valued VLSI processors, which are a signed-digit arithmetic VLSI processor, a residue arithmetic VLSI processor and a matching VLSI processor can achieve higher performance for real-world computing system.

Some new circuit configurations for dual-input integrators and differentiators are proposed. The use of a multiplier device around the Operational Amplifier (OA) yields electronic tunability of their time-constant (To) by a Control Voltage (Vx). Experimental results in support of theoretical design and analysis are included.

A new class of the universal representation for the positive integers is proposed. The positive integers are divided into infinite groups, and each positive integer n is represented by a pair of integers (p,q), which means that n is the q-th number in the p-th group. It is shown that the new class includes the message length strategy as a special case, and the asymptotically optimal representation can easily be realized. Furthermore, a new asymptotically and practically efficient representation scheme is proposed, which preserves the numerical, lexicographical, and length orders.

An accurate numerical solution is presented for the electromagnetic scattering from a double strip grating, where the strip planes are each supported by a dielectric slab. This structure is a model of polarization diplexers. The direction of propagation and the polarization of the incident plane wave are arbitrary. We derive a set of singular integral equations and solve it by the moment method, where the Chebyshev polynomials are successfully used as the basis and the testing functions. By numerical computations we examine the dependence of the diplexing properties on grating parameters in detail. The cross-polarization characteristics at skew incidence are also referred. From these results we construct an algorithm for the design of polarization diplexers.

Some problems in formal language theory are considered and are shown to be deterministic exponential time complete. They include the problems for a given context-free grammar G, a nondeterministic finite automaton M, a deterministic pushdown automaton MD, of determining whether L(G)L(M), and whether L(MD)L(M). Polynomial time reductions are presented from the pebble game problem, known to be deterministic exponential time complete, to each of these problems.

In this paper, a methodology for designing the architecture of the processor array for wide class of image processing algorithms is proposed. A concept of spatially expanding the SFG description which enables us to handle the problem as merely one-dimensional signal processing is used in constructing the methodology. Problem of I/O interface which is critical in real-time processing is also considered.

In this paper, four simple nonlinear circuits with time-varying resistors are analyzed. These circuits consist of only four elements; a inductor, a capacitor, a diode and a time-varying resistor and are a kind of parametric excitation circuits whose dissipation factors vary with time. In order to analyze chaotic phenomena observed from these circuits a degeneration technique is used, that is, diodes in the circuits are assumed to operate as ideal switches. Thereby the Poincar maps are derived as one-dimensional maps and chaotic phenomena are well explained. Moreover, validity of the analyzing method is confirmed theoretically and experimentally.

In a display system with a line-of-gaze (LOG) controller, it is difficult to make the directions and motions of a LOG-controlled object coincide as closely as possible in the display with the user's intended LOG-directions and motions. This is because LOG behavior is not only smooth, but also saccadic due to the problem of involuntary eye movement. This article introduces a flexible on-line LOG-control scheme to realize nearly perfect LOG operation. Using a mesh-wise cursor pattern, the first visual experiment elucidates subjectively that a Kalman Filter (KF) for smoothing and predicting is effective in filtering out macro-saccadic changes of the LOG and in predicting sudden changes of the saccade while movement is in progress. It must be assumed that the LOG trajectory can be described by a linear position-velocity-acceleration approximation of Sklansky Model (SM). Furthermore, the second experiment uses a four-point pattern and simulations to scrutinize the two physical properties of velocity and direction-changes of the LOG in order to quantitatively and efficiently resolve "moving" and "gazing". In order to greatly reduce the number of LOG-small-position changes while gazing, the proposed Gaze-Holding algorithm (GH) with a gaze-potential function is combined with the KF. This algorithm allows the occurrence frequency of the micro-saccade to be reduced from approximately 25 Hz to 1 or 2 Hz. This great reduction in the frequency of the LOG-controlled object moves is necessary to achieve the user's desired LOG-response while gazing. Almost perfect LOG control is accomplished by the on-line SM+KF+GH scheme while either gazing or moving. A menu-selection task was conducted to verify the effectiveness of the proposed on-line LOG-control method.

This paper presents a design of a new multiple-valued matching VLSI processor for high-speed reasoning. It is useful in the application for real-time rule-based systems with large knowledge bases which are programmable. In order to realize high-speed reasoning, the matching VLSI processor can perform the fully parallel pattern matching between an input data and rules. On the based of direct multiple-valued encoding of each attribute in an input data and rules, pattern matching can be described by using only a programmable delta literal. Moreover, the programmable delta literal circuit can be easily implemented using two kinds of floating-gate MOS devices whose threshold voltages are controllable. In fact, it is demonstrated that four kinds of threshold voltages in a practical floating-gate MOS device can be easily programmable by appropriately controlling the gate, the drain and the source voltage. Finally, the inference time of the quaternary matching VLSI processor with 256 rules and conflict resolution circuits is estimated at about 360 (ns), and the chip area is reduced to about 30 percent, in comparison with the equivalent binary implementation.

A fail-safe logic operation refers to such a processing operation that the output assumes the logical value zero when the operation circuit fails. The fail-safe multiple-valued logic operation is proposed as one method of logic operation. Section 2 defines the fail-asfe multiple-valued logic operation and presents an example of method for accomplishing the fail-safe multiple-valued logic operation. Section 3 describes the method of designing a fail-safe threshold operation device (window comparator) as basic device in the fail-safe multiple-valued logic operation in consideration of LSI implementation and shows an example of prototype fail-safe window comparator. This operation device has higher and lower thresholds. It oscillates and produces an operational output signal only when the input signal level falls between the higher and lower thresholds. Unless the fail-safe window comparator is supplied with input signals of higher voltage than the power supply voltage, it dose not form a feedbadk loop as required for it to oscillate. This characteristic prevents the device from erroneously producing an output signal when any failure occurs in the amplifiers comprising the oscillation circuit. The window comparator can be built as a fail-safe threshold operation device. The fail-safe characteristic is utilized in its LSI implementation. Section 4 verifies the fail-safe property of the prortotype fail-safe window comparator. It is shown that even when the LSI develops failures not evident from outsid (latent failures), it does not lose the operational function and maintains the fail-safe characteristic.

The current telecommunication network is structured in two layers: The intelligent layer that includes Intelligent Network (IN) nodes and Operation, Administration and Maintenance (OAM) nodes, and the transport layer that includes Network Elements (NEs). The transport layer carries user Information (Iu) from end-users as well as control and OAM Information (Ic&o) from IN/OAM nodes. The quick deployment of new IN services and OAM capabilities that will need (a) flexibility and easy management, and (b) an effective handling method for searching the huge amount of data among distributed databases, will be two requirements to be satisfied. Integrating various types of Ic&o into a unique Ic&o transport network and using ATM technique as a transport technique satisfies partly the requirement (a). To completely meet both requirements, this paper proposes the following solutions:(a) Intelligent layer connections and transport layer connections should be managed independently: The necessary mapping between the Logical Destination Address (LDA) that represents the logical address of the physical entity where data are routed, combined with the Quality Of Service (QOS) type, and the ATM connection IDentifier (ID), that is to say the Virtual Channel Identifier/ Virtual Path Identifier (VCI/VPI), is provided by specific nodes (the Ic&o network Management Nodes (Ic&o MNs)) belonging to an intermediate layer, i.e., the Ic&o network management layer.(b) The widely distributed aspect of the databases also needs a very effective data handling method. This paper proposes to implement a Distributed Directory System (DDS) into both intelligent nodes and Ic&o MNs.In order to apply the DDS function to 2 functional levels, the following items are studied: First, the possible mapping of DDS functions into the intelligent node functions is proposed. Second, this paper gives an interaction scenario between intelligent nodes and Ic&o MNs, to translate the LDA/QOS type into VPI/VCI. Finally, the analysis of the mapping of LDA/QOS type into VCI/VPI at the ATM level shows that the Ic&o network based on VP backbone offers the best compromise between flexibility, complexity and cost.

We examine the characteristics of the past successful m-valued I2L and ROMs that have been designed and we discuss the reasons of their success and withdraw. We look at the problems associated with scaling of m-valued CMOS current mode circuits. Then we discuss the tolerance issue, the respective propagation delays of binary and m-valued ICs and the interconnection issue. We conclude with the challenges for m-valued circuits in the competition with the exponential performance increase of binary circuits.

The Memory-Based Reasoning (MBR) is one of the mainstay approaches in massively parallel artificial intelligence research. However, it has not been explored from the viewpoint of hardware implementation. This paper demonstrates high robustness of the MBR, which is suitable for hardware implementation using Wafer Scale Integration (WSI) technology, and proposes a design of WSI-MBR hardware. The robustness is evaluated by a newly developed WSI-MBR simulator in the English pronunciation reasoning task, generally known as MBRTalk. The results show that defects or other fluctuations of device parameters have only minor impacts on the performances of the WSI-MBR. Moreover, it is found that in order to get higher reasoning accuracy, the size of the MBR database is much more crucial than the computation resolution. These features are proved to be caused by the fact that MBR does not rely upon each single data unit but upon a bulk data set. Robustness in the other MBR tasks can be evaluated in the same manner as discussed in this paper. The proposed WSI-MBR processor takes advantage of benefits discovered in the simulation results. The most area-demanding circuits--that is, multipliers and adders--are designed by analog circuits. It is expected that the 1.7 million processors will be integrated onto the 8-inch silicon wafer by the 0.3 µm SRAM technology.

This paper describes a text-independent speaker recognition method using predictive neural networks. For text-independent speaker recognition, an ergodic model which allows transitions to any other state, including selftransitions, is adopted as the speaker model and one predictive neural network is assigned to each state. The proposed method was compared to quantization distortion based methods, HMM based methods, and a discriminative neural network based method through text-independent speaker identification experiments on 24 female speakers. The proposed method gave the highest identification rate of 100.0%, and the effectiveness of predictive neural networks for representing speaker individuality was clarified.

We have developed a new functional MOS transistor called Neuron MOSFET (abbreviated as neuMOS or νMOS) which simulates the function of biological neurons. The new transistor is capable of executing a weighted sum calculation of multiple input signals and threshold operation based on the result of weighted summation, all in the voltage mode at a single transistor level. By utilizing its neuron-like very powerful functional capability, various circuits essential for multiple-valued logic operation have been designed using quite simple circuit configurations. The circuit designs for data conversion between the multivalued and binary logic systems and for generating universal literal functions are described and their experimental verifications are presented. One of the most important features of νMOS multivalued lagic circuit is that the circuit operates basically in the voltage mode, thus greatly reducing the power dissipation as compared to the conventional current mode circuitry. This is indeed most essential in implementing multivalued logic systems in ultra large scale integration. Another important feature of νMOS design is in its flexibility of implementing logic functions. The functional form of a universal literal function, for instance, can be arbitrarily altered by external signals without any modifications in its hardware configuration. A circuit representing multiple-valued multithreshold functions is also proposed.