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19941-19960hit(20498hit)

  • Boltzmann Machine Processor Using Single-Bit Operation

    Mamoru SASAKI  Shuichi KANEDA  Fumio UENO  Takahiro INOUE  Yoshiki KITAMURA  

     
    PAPER-Nonlinear Circuits and Neural Nets

      Vol:
    E76-A No:6
      Page(s):
    878-885

    This paper describes a single-bit parallel processor specified to Boltzmann Machine. The processor has SIMD (Shingle Instruction Multiple Data stream) type parallel architecture and every processing element (PE) has a single-bit ALU and a local memory storing connected weights between neurons. Features of the processor are large scale parallel processing a number of the simple single-bit PEs and effective expansion realized by multiple chips connected simple bus lines. Moreover, it is enhanced that the processing speed can be independent of the number of the neurons. We designed the PE using 1.2 µm CMOS process standard cells and confirmed the high performance using CAD simulations.

  • Error Probability Analysis in Reduced State Viterbi Decoding

    Carlos VALDEZ  Hiroyuki FUJIWARA  Ikuo OKA  Hirosuke YAMAMOTO  

     
    PAPER-Communication Theory

      Vol:
    E76-B No:6
      Page(s):
    667-676

    The performance evaluation by analysis of systems employing Reduced State Viterbi decoding is addressed. This type of decoding is characterized by an inherent error propagation effect, which yields a difficulty in the error probability analysis, and has been usually neglected in the literature. By modifying the Full State trellis diagram, we derive for Reduced State schemes, new transfer function bounds with the effects of error propagation. Both the Chernoff and the tight upper bound are applied to the transfer function in order to obtain the bit error probability upper bound. Furthermore, and in order to get a tighter bound for Reduced State decoding schemes with parallel transitions, the pairwise probability of the two sequences involved in an error event is upper bounded, and then the branch metric of a sequence taken from that bound is associated with a truncated instead of complete Gaussian noise probability density function. To support the analysis, particular assessment is done for a Trellis Coded Modulation scheme.

  • Antenna Gain Measurements in the Presence of Unwanted Multipath Signals Using a Superresolution Technique

    Hiroyoshi YAMADA  Yasutaka OGAWA  Kiyohiko ITOH  

     
    PAPER-Antennas and Propagation

      Vol:
    E76-B No:6
      Page(s):
    694-702

    A superresolution technique is considered for use in antenna gain measurements. A modification of the MUSIC algorithm is employed to resolve incident signals separately in the time domain. The modification involves preprocessing the received data using a spatial scheme prior to applying the MUSIC algorithm. Interference rejection in the antenna measurements using the fast Fourier transform (FFT) based techniques have been realized by a recently developed vector network analyzer, and its availability has been reported in the literature. However, response resolution in the time domain of these conventional techniques is limited by the antenna bandwidth. The MUSIC algorithm has the advantage of being able to eliminate unwanted responses when performing antenna measurements in situations where the antenna band-width is too narrow to support FFT based techniques. In this paper, experimental results of antenna gain measurements in a multipath environment show the accuracy and resolving power of this technique.

  • Toward the New Era of Visual Communication

    Masahide KANEKO  Fumio KISHINO  Kazunori SHIMAMURA  Hiroshi HARASHIMA  

     
    INVITED PAPER

      Vol:
    E76-B No:6
      Page(s):
    577-591

    Recently, studies aiming at the next generation of visual communication services which support better human communication have been carried out intensively in Japan. The principal motive of these studies is to develop new services which are not restricted to a conventional communication framework based on the transmission of waveform signals. This paper focuses on three important key words in these studies; "intelligent," "real," and "distributed and collaborative," and describes recent research activities. The first key word "intelligent" relates to intelligent image coding. As a particular example, model-based coding of moving facial images is discussed in detail. In this method, shape change and motion of the human face is described by a small number of parameters. This feature leads to the development of new applications such as very low bit-rate transmission of moving facial images, analysis and synthesis of facial expression, human interfaces, and so on. The second key word "real" relates to communication with realistic sensations and virtual space teleconferencing. Among various component technologies, real-time reproduction of 3-D human images and a cooperative work environment with virtual space are discussed in detail. The last key word "distributed and collaborative" relates to collaborative work in a distributed work environment. The importance of visual media in collaborative work, a concept of CSCW, and requirements for realizing a distributed collaborative environment are discussed. Then, four examples of CSCW systems are briefly outlined.

  • Parallel Viterbi Decoding Implementation by Multi-Microprocessors

    Hui ZHAO  Xiaokang YUAN  Toru SATO  Iwane KIMURA  

     
    PAPER-Communication Theory

      Vol:
    E76-B No:6
      Page(s):
    658-666

    The Viterbi algorithm is a well-established technique for channel and source decoding in high performance digital communication systems. However, excessive time consumption makes it difficult to design an efficient high-speed decoder for practical application. This paper describes the implementation of parallel Viterbi algorithm by multi-microprocessors. Internal computations are performed in a parallel fashion. The use of microprocessors allows low-cost implementation with moderate complexity. The software and hardware implementations of the Viterbi algorithm on parallel multi-microprocessors for real-time decoding are presented. The implemented method is based on a combination of forming a set of tables and calculations. For efficient operation under fully parallel Viterbi decoding by microprocessors, we considered: (1) branch metrics processing, path metrics updating, path memory updating and decoding output for microprocessor, (2) efficient decomposition of the sequential Viterbi algorithm into parallel algorithms, (3) minimization of the communication among the microprocessors. The practical solutions for the problems of synchronization among the miroprocessors, interconnection network for communication among the microprocessors and memory management are discussed. Furthermore the performance and the speed of the parallel Viterbi decoding are given. For a fixed processing speed of given hardwares, parallel Viterbi decoding allows a linear speed up in the throughput rate with a linear increase in hardware complexity.

  • Critical Slice-Based Fault Localization for Any Type of Error

    Takao SHIMOMURA  

     
    PAPER-Software Systems

      Vol:
    E76-D No:6
      Page(s):
    656-667

    Existing algorithmic debugging methods which can locate faults under the guidance of a system have a number of shortcomings. For example, some cannot be applied to imperative languages with side effects; some can locate a faulty function but cannot locate a faulty statement; and some cannot detect faults related to missing statements. This paper presents an algorithmic critical slice-based fault-locating method for imperative languages. Program faults are first classified into two categories: wrong-value faults and missing-assignment faults. The critical slice with respect to a variable-value error is a set of statements such that (1) a wrong-value fault contained in any instruction in the critical slice may have caused that variable-value error, and (2) a wrong-value fault contained in any instruction outside the critical slice could never have caused that variable-value error. The paper also classifies errors found during program testing into three categories: wrong-output errors, missing-output errors, and infinite-loop errors with no output. It finally shows that it is possible to algorithmically locate any fault, including missing statements, for each type of error.

  • Behavior of Solutions Related to an Accuracy Exp(-1/ε)

    Makoto ITOH  

     
    PAPER-Nonlinear Circuits and Neural Nets

      Vol:
    E76-A No:6
      Page(s):
    867-872

    Behavior of solutions related to an accuracy exp(-1/ε) is studied. Computer results are given, and examined from the view-point of non-standard analysis. The experimental results raise some important questions on the computer study of slow-fast systems.

  • 3-D Object Recognition System Based on 2-D Chain Code Matching

    Takahiro HANYU  Sungkun CHOI  Michitaka KANEYAMA  Tatsuo HIGUCHI  

     
    PAPER-Methods and Circuits for Signal Processing

      Vol:
    E76-A No:6
      Page(s):
    917-923

    This paper presents a new high-speed three-dimensional (3-D) object recognition system based on two-dimensional (2-D) chain code matching. An observed 3-D object is precisely represented by a 2-D chain code sequence from the discrete surface points of the 3-D object, so that any complex objects can be recognized precisely. Moreover, the normalization procedures such as translation, rotation of 3-D objects except scale changes can be performed systematically and regularly regardless of the complexity of the shape of 3-D objects, because almost all the normalization procedures of 3-D objects are included in the 2-D chain code matching procedure. As a result, the additional normalization procedure become only the processing time for scale changes which can be performed easily by normalizing the length of the chain code sequence. In addition, the fast fourier transformation (FFT) is applicable to 2-D chain code matching which calculates cross correlation between an input object and a reference model, so that very fast recognition is performed. In fact, it is demonstrated that the total recognition time of a 3-D ofject is estimated at 5.35 (sec) using the 28.5-MIPS SPARC workstation.

  • Noise Temperature of Active Feedback Resonator (AFR)

    Youhei ISHIKAWA  Sadao YAMASHITA  Seiji HIDAKA  

     
    PAPER

      Vol:
    E76-C No:6
      Page(s):
    925-931

    An active feedback resonator (AFR) is a kind of circuit which functions as a high unloaded Q resonator. The AFR employs an active feedback loop which compensates for the energy loss of a conventional microwave resonator. Owing to an active element in the AFR, thermal noise should be taken into account when designing the AFR. In order to simplify a circuit design using the AFR we introduced noise temperature (Tn) for the AFR. In addition, we describe the AFR design which gives minimum noise temperature. Finally, the noise temperature, measured in an AFR as a band elimination filter, is compared with the theoretical value to evaluate the AFR.

  • Recessed-Gate Doped-Channel Hetero-MISFETs (DMTs) for High-Speed Laser Driver IC Application

    Yasuyuki SUZUKI  Hikaru HIDA  Tetsuyuki SUZAKI  Sadao FUJITA  Akihiko OKAMOTO  

     
    PAPER

      Vol:
    E76-C No:6
      Page(s):
    907-911

    Recessed-gate DMTs (doped-channel hetero-MISFETs) with i-AlGaAs/n-GaAs structure and pseudomorphic i-AlGaAs/n-InGaAs/i-GaAs structure have been developed. Broad plateaus in gm and fT provide evidence that the DMTs make the devices suitable for high-speed large-signal operation. GaAs DMTs with 0.35 µm-length have gate turn on voltage of 0.7 V, maximum transconductance of 320 mS/mm and fT of 41 GHz. Pseudomorphic DMTs have gate turn on voltage of 0.9 V, maximum transconductance of 320 mS/mm, fT of 42 GHz and have the enhanced advantages of high current drivability and large gate swing. Further more, with the use of the recessed-gate DMTs, a high-speed laser driver IC for multi-Gb/s optical communication systems are demonstrated. This laser driver IC operates at 10 Gb/s with rise and fall times as fast as 40 psec, and it can drive up to 60 mA into a 25 Ω load.

  • Cancellation Technique of Parasitics in Active Filter Design

    Takao TSUKUTAKI  Masaru ISHIDA  Yutaka FUKUI  

     
    LETTER-Methods and Circuits for Signal Processing

      Vol:
    E76-A No:6
      Page(s):
    957-960

    This letter presents a technique to cancel the parasitic effects of operational amplifier (op amp) in active filter design. To minimize the effects, an op amp model considering the parasitics (i.e. both parasitic poles and zeros) is utilized. It is shown that undesirable factors in the transfer function due to the parasitics can be canceled well by predistorting the passive element values of the circuit. As an example, an active-R highpass filter is evaluated both theoretically and numerically. In this way, the proposed technique can be effectively incorporated into the design of active filters.

  • A 156-Mb/s Interface CMOS LSI for ATM Switching Systems

    Takahiko KOZAKI  Kiyoshi AIKI  Makoto MORI  Masao MIZUKAMI  Ken'ichi ASANO  

     
    PAPER-Communication Device and Circuit

      Vol:
    E76-B No:6
      Page(s):
    684-693

    This paper describes a 0.8-µm CMOS LSI developed for a 156-Mb/s serial interface in ATM switching systems. Recently, there have been increasing problems of connector pin neck and higher power consumption when enhancing switching system capacity. To overcome these problems, we have developed an LSI with a high-speed interface by using CMOS technology to achieve low power consumption. A low-swing differential signal level is used to achieve 156-Mb/s data transmission. We named this new circuit technique ALTS (Advanced Low-level Transmission circuit System). Using the LSI, transmission can be achieved between boards or racks through a 10-meter twisted pair cable. The LSI has a 156-Mb/s transmitter-receiver, a serial-to-parallel converter and a parallel-to-serial converter. It performs 19.5-Mb/s parallel data/156-Mb/s serial data conversion and 156-Mb/s serial data transmission. In addition, it has a bit phase synchronizer and cell synchronizer, which enables it to transmit and synchronize serial data without a paralleled clock or a paralleled cell top signal, by distributing a common 156-MHz clock and a common cell top signal to the whole system. We evaluated the bit error rate and timing margin on data transmission under several conditions. The results show that we can apply this LSI to commercially available ATM switching systems. This paper also describes methods of expanding switch capacity and transmitting 624-Mb/s data using this LSI.

  • A Frequency Utilization Ffficiency Improvement on Superposed SSMA-QPSK Signal Transmission over High Speed QPSK Signals in Nonlinear Channels

    Takatoshi SUGIYAMA  Hiroshi KAZAMA  Masahiro MORIKURA  Shuji KUBOTA  Shuzo KATO  

     
    PAPER

      Vol:
    E76-B No:5
      Page(s):
    480-487

    This paper proposes a superposed SSMA (Spread Spectrum Multiple Access)-QPSK (Quadrature Phase Shift Keying) signal transmission scheme over high speed QPSK signals to achieve higher frequency utilization efficiency and to facilitate lower power transmitters for SSMA-QPSK signal transmission. Experimental results show that the proposed scheme which employs the coding-rate of one-half FEC (Forward Error Correction) and a newly proposed co-channel interference cancellation scheme for SSMA-QPSK signals can transmit twenty SSMA-QPSK channels simultaneously over a nonlinearly amplified high speed QPSK signal transmission channel and achieve as ten times SSMA channels transmission as that without co-channel interference cancellation when the SSMA-QPSK signal power to the high speed QPSK signal power ratio equals -30dB. Moreover, cancellation feasibility generation of the interference signals replica through practical hardware implementation is clarified.

  • Design Considerations for Low-Voltage Crystal Oscillator Circuit in a 1.8-V Single Chip Microprocessor

    Shigeo KUBOKI  Takehiro OHTA  Junichi KONO  Yoji NISHIO  

     
    PAPER

      Vol:
    E76-C No:5
      Page(s):
    701-707

    A low-voltage, high-speed 4-bit CMOS single chip microprocessor, with instruction execution time of 1.0µs at a power supply voltage of 1.8V, has been developed. A single chip processor generally includes crystal oscillation circuits to generate a system clock or a time-base clock. But when the operating voltage is lowered, it becomes difficult to get oscillations to start reliably and to continue stably. This paper describes a low voltage circuit design method for built-in crystal oscillators. Simple design equations for oscillation starting voltage and oscillation starting time are introduced. Then effects of the circuit device parameters, such as power supply voltage, loop gain values, and subthreshold swing S, on the low voltage performance of the crystal oscillators are considered. It is shown that the crystal oscillators operate in a tailing (subthreshold) region at voltages lower than about 1.8 V. Subthreshold swing, threshold voltage, and open loop gain have a significant influence on low voltage oscillation capability. This design method can be applied to crystal oscillators for a wide range of operating voltages.

  • Safety Control of Power Press by Using Fail-Safe Multiple-Valued Logic

    Masayoshi SAKAI  Masakazu KATO  Koichi FUTSUHARA  Masao MUKAIDONO  

     
    PAPER-Fail-Safe/Fault Tolerant

      Vol:
    E76-D No:5
      Page(s):
    577-585

    This paper first clarifies the logic construction of safety control for the operation of a power press and then describes fail-safe dual two-rail system signal processing and fail-safe multiple-valued logic operations as methods for achieving this control as a fail-safe system. It finally shows a circuit for generating fail-safe two-rail run button signals based on ternary logic for concrete operation of the power press and an operation control circuit for confirming brake performance for each cycle of slide operation by using the run button signals. The control circuit uses such multiple-valued logic operations that binary logic signals that do not erroneously go logic 1 are added to a multiple-valued logic signal and the multiple-valued logic signal is converted to a binary logic signal that does not erroneously go logic 1 by a threshold operation.

  • Environment-Dependent Self-Organization of Positional Information in Coupled Nonlinear Oscillator System--A New Principle of Real-Time Coordinative Control in Biological Distributed System--

    Yoshihiro MIYAKE  Yoko YAMAGUCHI  Masafumi YANO  Hiroshi SHIMIZU  

     
    LETTER-Neural Nets--Theory and Applications--

      Vol:
    E76-A No:5
      Page(s):
    780-785

    The mechanism of environment-dependent self-organization of "positional information" in a coupled nonlinear oscillator system is proposed as a new principle of realtime coordinative control in biological distributed system. By modeling the pattern formation in tactic response of Physarum plasmodium, it is shown that a global phase gradient pattern self-organized by mutual entrainment encodes not only the positional relationship between subsystems and the total system but also the relative relationship between internal state of the system and the environment.

  • On a Logic Based on Graded Modalities

    Akira NAKAMURA  

     
    PAPER-Logic and Logic Functions

      Vol:
    E76-D No:5
      Page(s):
    527-532

    The purpose of this paper is to offer a modal logic which enables us symbolic reasoning about data, especially, fuzzy relations. For such a purpose, the present author provided some systems of modal fuzzy logic. As a continuous one of those previous works, a logic based on the graded modalities is proposed. After showing some properties of this logic, the decision procedure for this logic is given in the rectangle method.

  • A Link Study of a Low-Earth Orbit Satellite Communications System Using Optical Intersatellite Links

    Mitsuo NOHARA  Yoshinori ARIMOTO  Wataru CHUJO  Masayuki FUJISE  

     
    PAPER

      Vol:
    E76-B No:5
      Page(s):
    536-543

    Link conditions of a low-earth orbit (LEO) satellite communications system were evaluated, to provide the information necessary for designing a broadband LEO-SAT communications system. The study was made both for optical intersatellite and user/satellite links. For the optical intersatellite link (ISL), we examined several ISL configurations in a circular polar orbit, and found that when the satellites are in the same orbital plane, the link parameters are quite stable, that is, the link between adjacent satellites can be regarded as fixed and, therefore, suitable for broadband transmission via an optical link. However, the link conditions between adjacent orbits change very quickly and over a wide range. To overcome this and extend the network path between satellites in adjacent orbital planes, we proposed intermittent use of the link between satellites in co-rotating adjacent orbital planes at the low latitude region, i.e., only during the period of stable conditions. The optical intersatellite link budget also sets link parameters that are realistic, given present optoelectronic technologies. From quantitative evaluations of the user/satellite link, we believe that both the satellite altitude and minimum elevation angle are critical, both in defining the quality of the service of the LEO-SAT system and in their impact on the other transmission parameters. The link loss, the visible period and the required number of satellites vs. satellite altitude and elevation angle are also indicated. These are important considerations for future system design.

  • A Differential-Geometrical Theory of Sensory System --Relations between the Psychophysical, the DL and the JND Functions

    Ryuzo TAKIYAMA  

     
    PAPER-Mathematical Theory

      Vol:
    E76-A No:5
      Page(s):
    683-688

    This paper discusses psychophysical aspects of human sensory system through a differential-geometrical formulation. The discussions reveal relationships among three fundamental functions--the psychophysical, the DL and the JND functions, which characterize sensory system.

  • Standardization of Telemetry Signal Transmission by CCSDS and an Experiment Using a Satellite in a Highly Elliptical Orbit

    Tadashi TAKANO  Takahiro YAMADA  Koshiro SHUTO  Toshiyuki TANAKA  Katherine I. MOYD  

     
    REVIEW PAPER

      Vol:
    E76-B No:5
      Page(s):
    466-472

    The Consultative Committee of Space Data Systems (CCSDS) proposes a packetized telemetry scheme for the convenience of data exchange and networking in space activity. This paper describes the outline of the telemetry scheme and the on-orbit experiment which was carried out to show the applicability of the proposed CCSDS packet telemetry scheme using the Japan's satellite "Hiten" in a highly elliptical orbit. The telemetry data which are generated by the onboard instruments are packetized in Hiten, and reformed to the original data in earth stations successfully. The experimental results show that the standardized scheme is helpful for tracking cross-support between organizations, and that the concatenated code is quite effective to transmit data in a low C/N condition.

19941-19960hit(20498hit)