This paper proposes physical channel structures and a cell search method for OFDM based radio access in the Evolved UTRA (UMTS Terrestrial Radio Access) downlink, which supports multiple scalable transmission bandwidths from 1.25 to 20 MHz. In the proposed physical channel structures, the central sub-carrier of the OFDM signal is located on the frequency satisfying the 200-kHz raster condition regardless of the transmission bandwidth of the cell site. Moreover, the synchronization channel (SCH) and broadcast channel (BCH), which are necessary for cell search, are transmitted in the central part of the entire transmission spectrum with a fixed bandwidth. In the proposed cell search method, a user equipment (UE) acquires the target cell in the cell search process in the initial or connected mode employing the SCH and possibly the reference signal, which are transmitted in the central part of the given transmission bandwidth. After detecting the target cell, the UE decodes the common control information through the BCH, which is transmitted at the same frequency as the SCH, and identifies the transmission bandwidth of the cell to be connected. Computer simulations show the fast cell search performance made possible by using the proposed SCH structure and the cell search method.

For coherent detection, decoding Orthogonal Space-Time Block Codes (OSTBC) requires full channel state information at the receiver, which basically is obtained by channel estimation. However, in practical systems, channel estimation errors are inevitable and may degrade the system performance more as the number of antennas increases. This letter shows that, using fewer receive antennas can enhance the performance of OSTBC systems in presence of channel estimation errors. Furthermore, a novel adaptive receive antenna selection scheme, which adaptively adjusts the number of receive antennas, is proposed. Performance evaluation and numerical examples show that the proposed scheme improves the performance obviously.

High power consumption is a constraining factor for the growth of programmable logic devices. We propose two techniques in order to reduce power consumption. The first is a technique for creating contexts. This technique uses data-dependent circuits and wire sharing between contexts. The second is a technique for switching the contexts. In this paper, we evaluate the capability of the two techniques to reduce power consumption using a multi-context logic device. As a result, as compared with the original circuit, our multi-context circuits reduced the power consumption by 9.1% on an average and by a maximum of 19.0%. Furthermore, applying our resource sharing technique to these circuits, we achieved a reduction of 10.6% on an average and a maximum reduction of 18.8%.

Most learning-based super-resolution methods neglect the illumination problem. In this paper we propose a novel method to combine blind single-frame super-resolution and shadow removal into a single operation. Firstly, from the pattern recognition viewpoint, blur identification is considered as a classification problem. We describe three methods which are respectively based on Vector Quantization (VQ), Hidden Markov Model (HMM) and Support Vector Machines (SVM) to identify the blur parameter of the acquisition system from the compressed/uncompressed low-resolution image. Secondly, after blur identification, a super-resolution image is reconstructed by a learning-based method. In this method, Logarithmic-wavelet transform is defined for illumination-free feature extraction. Then an initial estimation is obtained based on the assumption that small patches in low-resolution space and patches in high-resolution space share a similar local manifold structure. The unknown high-resolution image is reconstructed by projecting the intermediate result into general reconstruction constraints. The proposed method simultaneously achieves blind single-frame super-resolution and image enhancement especially shadow removal. Experimental results demonstrate the effectiveness and robustness of our method.

Multiple sequence alignment problems in computational biology have been focused recently because of the rapid growth of sequence databases. By computing alignment, we can understand similarity among the sequences. Many hardware systems for alignment have been proposed to date, but most of them are designed for two-dimensional alignment (alignment between two sequences) because of the complexity to calculate alignment among more than two sequences under limited hardware resources. In this paper, we describe a compact system with an off-the-shelf FPGA board and a host computer for more than three-dimensional alignment based on dynamic programming. In our approach, high performance is achieved (1) by configuring optimal circuit for each dimensional alignment, and (2) by two phase search in each dimension by reconfiguration. In order to realize multidimensional search with a common architecture, two-dimensional dynamic programming is repeated along other dimensions. With this approach, we can minimize the size of units for alignment and achieve high parallelism. Our system with one XC2V6000 enables about 300-fold speedup as compared with single Intel Pentium4 2 GHz processor for four-dimensional alignment, and 100-fold speedup for five-dimensional alignment.

Our purpose is to estimate conditional probabilities of output labels in multiclass classification problems. Adaboost provides highly accurate classifiers and has potential to estimate conditional probabilities. However, the conditional probability estimated by Adaboost tends to overfit to training samples. We propose loss functions for boosting that provide shrinkage estimator. The effect of regularization is realized by shrinkage of probabilities toward the uniform distribution. Numerical experiments indicate that boosting algorithms based on proposed loss functions show significantly better results than existing boosting algorithms for estimation of conditional probabilities.

Extracting frequently executed (hot) portions of the application and executing their corresponding data flow graph (DFG) on the hardware accelerator brings about more speedup and energy saving for embedded systems comprising a base processor integrated with a tightly coupled accelerator. Extending DFGs to support control instructions and using Control DFGs (CDFGs) instead of DFGs results in more coverage of application code portion are being accelerated hence, more speedup and energy saving. In this paper, motivations for extending DFGs to CDFGs and handling control instructions are introduced. In addition, basic requirements for an accelerator with conditional execution support are proposed. Then, two algorithms are presented for temporal partitioning of CDFGs considering the target accelerator architectural constraints. To demonstrate effectiveness of the proposed ideas, they are applied to the accelerator of a reconfigurable processor called AMBER. Experimental results approve the remarkable effectiveness of covering control instructions and using CDFGs versus DFGs in the aspects of performance and energy reduction.

A metallic waveguide with dual in-line dielectric rods can propagate electromagnetic waves more than two times higher than the cutoff frequency region and without higher modes [1]. If the straight portion in the waveguide has even symmetry, then dielectric rods are only required in the bent portion. Connection losses between the portions are improved by adding other dielectric rods.

The fixed charge transportation problem (FCTP) is a classic challenge for combinatorial optimization; it is based on the well-known transportation problem (TP), and is one of the prime examples of an NP-complete variant of the TP, of general importance in a wide range of transportation network design problems. Many techniques have been applied to this problem, and the most effective so far (in terms of near-optimal results in reasonable time on large instances) are evolutionary algorithm based approaches. In particular, an EA proposed by Eckert and Gottlieb has produced the best performance so far on a set of specific benchmark instances. We introduce a new scheme, which has more general applicability, but which we test here on the FCTP. The proposed scheme applies an adaptive mutation process immediately following the evaluation of a phenotype. It thereby adapts automatically to learned information encoded in the chromosome. The underlying encoding approach is to encode an ordering of elements for interpretation by a constructive algorithm (such as with the Link and Node Biased encoding for spanning trees, and the Random Keys encoding which has been applied to both scheduling and graph problems), however the main adaptive process rewards links in such a way that genes effectively encode a measure of the number of times their associated link has appeared in selected solutions. Tests are done which compare our approach with Eckert and Gottlieb's results on benchmark FCTP instances, and other approaches.

Closed-form expressions for a crosstalk noise amplitude and worst-case delay in capacitively coupled two-line and three-line systems are derived assuming bus lines and other signal lines in a VLSI. Two modes are studied; a case that adjacent lines are driven from the same direction, and the other case that adjacent lines are driven from the opposite direction. Beside, a junction capacitance of a driver MOSFET is considered. The closed-form expressions are useful for circuit designers in an early stage of a VLSI design to give insight to interconnection problems. The expressions are extensively compared and fitted to SPICE simulations. The relative and absolute errors in the crosstalk noise amplitude are within 63.8% and 0.098 E (where E is a supply voltage), respectively. The relative error in the worst-case delay is less than 8.1%.

In these days, many dynamically reconfigurable architectures have been introduced to fill the gap between ASICs and software-programmed processors such as GPPs and DSPs. These reconfigurable architectures have shown to achieve higher performance compared to software-programmed processors. However, reconfigurable architectures suffer from a significant reconfiguration overhead and a speedup limitation. By reducing the reconfiguration overhead, the overall performance of reconfigurable architectures can be improved. Therefore, we will describe temporal partitioning, which are able to amortize the reconfiguration overhead at synthesis phase or compilation time. Our temporal partitioning methodology splits a configuration context into temporal partitions to amortize reconfiguration overhead. And then, we will present benchmark results to demonstrate the effectiveness of our methodology.

SIMD instructions are often implemented in modern multimedia oriented processors. Although SIMD instructions are useful for many digital signal processing applications, most compilers do not exploit SIMD instructions. The difficulty in the utilization of SIMD instructions stems from data parallelism in registers. In assembly code generation, the positions of data in registers must be noted. A technique of generating pack instructions which pack or reorder data in registers is essential for exploitation of SIMD instructions. This paper presents a code generation technique for SIMD instructions with pack instructions. SIMD instructions are generated by finding and grouping the same operations in programs. After the SIMD instruction generation, pack instructions are generated. In the pack instruction generation, Multi-valued Decision Diagram (MDD) is introduced to represent and to manipulate sets of packed data. Experimental results show that the proposed code generation technique can generate assembly code with SIMD and pack instructions performing repacking of 8 packed data in registers for a RISC processor with a dual-issue coprocessor which supports SIMD and pack instructions. The proposed method achieved speedup ratio up to about 8.5 by SIMD instructions and multiple-issue mechanism of the target processor.

In this paper, we investigate the critical low coverage problem of position aware localized efficient broadcast in mobile ad hoc ubiquitous sensor networks and propose a generic framework for it. The framework is to determine a small subset of nodes and minimum transmission radiuses based on snapshots of network state (local views) along the broadcast process. To guarantee the accuracy of forward decisions, based on historical location information nodes will predict neighbors' positions at future actual transmission time and then construct predicted and synchronized local views rather than simply collect received "Hello" messages. Several enhancement technologies are also proposed to compensate the inaccuracy of prediction and forward decisions. To verify the effectiveness of our framework we apply existing efficient broadcast algorithms to it. Simulation results show that new algorithms, which are derived from the generic framework, can greatly increase the broadcast coverage ratio.

Sensor networks are often deployed in unattended environments, thus leaving these networks vulnerable to false data injection attacks in which an adversary injects forged reports into the network through compromised nodes, with the goal of deceiving the base station or depleting the resources of forwarding nodes. Several research solutions have been recently proposed to detect and drop such forged reports during the forwarding process. Each design can provide the equivalent resilience in terms of node compromising. However, their energy consumption characteristics differ from each other. Thus, employing only a single filtering scheme for a network is not a recommendable strategy in terms of energy saving. In this paper, we propose a fuzzy-based adaptive filtering scheme selection method for energy saving. A fuzzy rule-based system is exploited to choose one of three filtering schemes by considering the false traffic ratio, the security threshold value, distance, and the detection power of the filtering scheme. The adaptive selection of the filtering schemes can conserve energy, and guarantee sufficient resilience.

In 1995, Vanstone and Zuccherato proposed a novel method of generating RSA moduli having a predetermined set of bits which are the ASCII representation of user's identification information (i.e., name, email address, etc.). This could lead to a savings in bandwidth for data transmission and storage. In this paper, we apply this idea of Vanstone and Zuccherato for reducing the storage requirement of RSA public moduli to integer factoring based public-key schemes with their moduli of the form prq. More precisely, we explicitly propose two efficient methods for specifying high-order bits of prime factors of their public-keys. We also consider the security of the proposed methods.

In this paper, we address the issue of mobile positioning and tracking after measurements have been made on the distances and possibly directions between an MS (mobile station) and its nearby base stations (BS's). The measurements can come from the time of arrival (TOA), the time sum of arrival (TSOA), the time difference of arrival (TDOA), and the angle of arrival (AOA). They are in general corrupted with measurement noise and NLOS (non-line-of-sight) error. The NLOS error is the dominant factor that degrades the accuracy of mobile positioning. Assuming specific statistic models for the NLOS error, however, we propose a scheme that significantly reduces its effect. Regardless of which of the first three measurement types (i.e. TOA, TSOA, or TDOA) is used, the proposed scheme computes the MS location in a mathematically unified way. We also propose a method to identify the TOA measurements that are not or only slightly corrupted with NLOS errors. We call them nearly NLOS-error-free TOA measurements. From the signals associated with TOA measurements, AOA information can be obtained and used to aid the MS positioning. Finally, by combining the proposed MS positioning method with Kalman filtering, we propose a scheme to track the movement of the MS.

Ubiquitous sensor networks (USNs) are comprised of energy constrained nodes. This limitation has led to the crucial need for energy-aware protocols to produce an efficient network. We propose a sleep scheduling scheme for balancing energy consumption rates in a single hop cluster based network using Analytical Hierarchy Process (AHP). We consider three factors contributing to the optimal nodes scheduling decision and they are the distance to cluster head (CH), residual energy, and sensing coverage overlapping, respectively. We also propose an integrated sleep scheduling and geographical multi-path routing scheme for USNs by AHP. The sleep scheduling is redesigned to adapt the multi-hop case. For the proposed routing protocol, the distance to the destination location, remaining battery capacity, and queue size of candidate sensor nodes in the local communication range are taken into consideration for next hop relay node selection. The proposed schemes are observed to improve network lifetime and conserve energy without compromising desired coverage. In the multi-hop case, it can further reduce the packet loss rate and link failure rate since the buffer capacity is considered.

This letter presents a new vertical Bell Labs layered space-time (V-BLAST) transmission scheme for developing low-complexity tree searching in the QRD-M algorithm. In the new V-BLAST system, we assign modulation scheme in ascending order from top to bottom tree branches. The modulation set to be assigned is decided by two criteria: minimum performance loss and maximum complexity reduction. We also propose an open-loop power allocation algorithm to surmount the performance loss. Numerical results show that the proposed V-BLAST transmission approach can significantly reduce the computational loads of the QRD-M algorithm with a slight performance degradation.

A new algorithm is proposed to reduce the area of a pipelined circuit using a combination of multi-clock cycle paths, clock scheduling and delay balancing. The algorithm analyzes the circuit and replaces intermediate registers with delay elements under the condition that the circuit works correctly at given target clock-period range with the smaller area. Experiments with pipelined multipliers verify that the proposed algorithm can reduce the area of a pipelined circuit without degrading performance.

This paper presents a study to estimate the composition of an electric load, i.e. to determine the amount of each load class by the direct measurements of the total electric current waveform from instrument reading. Kalman filter algorithm is applied to estimate the electric load composition on a consumer side of a distributed power system. The electric load supplied from the different voltage level by using a non-ideal delta-wye transformer is also studied with consideration of the practical environment for a distributed power system.