The traditional way of approaching device-level placement problems for analog layout is to explore a huge search space of absolute placement representations, where cells are allowed to illegally overlap during their moves. This paper presents a novel exploration technique for analog placement, operating on a subset of tree representations of the layout, where the typical presence of an arbitrary number of symmetry groups of devices is directly taken into account during the search of the solution space. The efficiency of the novel approach is due to the use of red-black interval trees, data structures employed to support operations on dynamic sets of intervals.

The application of fault injection in the context of dependability benchmarking is far from being straightforward. One decisive issue to be addressed is to what extent injected faults are representative of the considered faults. This paper proposes an approach to analyze the effects of real and injected faults.

A Java execution environment is implemented, in which a hardware engine is operated in parallel with an embedded processor. This pair of hardware facilities together with an additional software kernel are devised for existing embedded systems, so as to execute Java applications more efficiently in such a way that 39 instructions are added to the original Java Virtual Machine to implement the software kernel. The exploration of design parameters is also attempted to attain a low hardware cost and high performance. The proposed hardware engine of a 6-stage pipeline can be integrated in a single chip using 30 k gates together with the instruction and data cache memories. The proposed approach improves the execution speed by a factor of 5 in comparison with the J2ME software implementation.

Recently, wireless networks have become a major sector in the telecommunication industry. More and more applications seek to become wireless. However, a major obstacle in adapting wired applications to wireless is the quality of service problem. Although the wireless bandwidth is improving at a fast pace, it still is not enough for modern multimedia applications. Even if we solve the bandwidth problem, the mobility of users also poses challenges for QoS provision. If the user moves randomly, how and where can resources be reserved in advance for roaming users to move smoothly and seamlessly? In this paper, we propose a method for predictive resource reservation in wireless networks. Resources reserved but not used will seriously affect the system performance. Therefore, we also have mechanisms to release the reserved resources when it is not used within a time limit and allow resources to be used temporarily by another mobile user. We compare the performance of our method with those of fixed allocation scheme and shadow cluster scheme. The results indicate its effectiveness and feasibility.

In relation to the Software Defined Radio (SDR) concept, an experimental simulation system was developed. Likewise, verification tests were performed in order to validate the envisaged SDR certification processes including its development, certification, distribution, and software installation assuming the future possibility of exchanging the software in the field.

The problem of calculating parasitic capacitances between two interconnects is investigated dedicatedly for liquid crystal displays, with the main focus put on the approximate expressions of the capacitances caused at the intersection and the parallel running of two interconnects. To derive simple and accurate approximate expressions, the interconnects in these structures are divided into a few basic coupling regions in such a way that the electro-magnetic field in each region can be calculated by a 2-D capacitance model. Then the capacitance in such a region is represented by a simple expression adjusted to the results computed by an electro-magnetic field solver. The total capacitance obtained by summing the capacitances in all regions is evaluated in comparison with the one obtained by using a 3-D field solver, resulting in a relative error of less than 5%.

The High-Low Water Mark destage (HLWM) algorithm is widely used to enable cached RAID5 to flush dirty data from its write cache to disks due to the simplicity of its operations. It starts and stops a destaging process based on the two thresholds that are configured at the initialization time with the best knowledge of its underlying storage performance capability and its workload pattern which includes traffic intensity, access patterns, etc. However, each time the current workload varies from the original, the thresholds need to be re-configured with the changed workload. This paper proposes an efficient destage algorithm which automatically re-configures its initial thresholds according to the changed traffic intensity and access patterns, called adaptive thresholding. The core of adaptive thresholding is to define the two thresholds as the multiplication of the referenced increasing and decreasing rates of the write cache occupancy level and the time required to fill and empty the write cache. We implement the proposed algorithm upon an actual RAID system and then verify the ability of the auto-reconfiguration with synthetic workloads having a different level of traffic intensity and access patterns. Performance evaluations under well-known traced workloads reveal that the proposed algorithm reduces disk IO traffic by about 12% with a 6% increase in the overwrite ratio compared with the HLWM algorithm.

A negative thermal expansion ceramic substrate and an athermal fiber Bragg grating component with the substrate were subjected to reliability tests. We confirmed that the component has adequate durability for use as optical filters in the WDM system, under test conditions of damp heat, low temperature, mechanical shock and vibration. (50 words)

Because most link-state routing protocols, such as OSPF and IS-IS, calculate routes using the Dijkstra algorithm, which poses scalability problems, implementors often introduce an artificial delay to reduce the number of route calculations. Although this delay directly affects IP packet forwarding, it can be acceptable when the network topology does not change often. However, when the topology of a network changes frequently, this delay can lead to a complete loss of IP reachability for the affected network prefixes during the unstable period. In this paper, we propose the Cached Shortest-path Tree (CST) approach, which speeds up intra-domain routing convergence without extra execution of the Dijkstra algorithm, even if the routing for a network is quite unstable. The basic idea of CST is to cache shortest-path trees (SPTs) of network topologies that appear frequently, and use these SPTs to instantly generate a routing table when the topology after a change matches one in the caches. CST depends on a characteristic that we found from an investigation of routing instability conducted on the WIDE Internet in Japan. That is, under unstable routing conditions, both frequently changing Link State Advertisements (LSAs) and their instances tend to be limited. At the end of this paper, we show CST's effectiveness by a trace-driven simulation.

Critical path selection is an indispensable step for AC delay test and timing validation. Traditionally, this step relies on the construction of a set of worse-case paths based upon discrete timing models. However, the assumption of discrete timing models can be invalidated by timing defects and process variation in the deep sub-micron domain, which are often continuous in nature. As a result, critical paths defined in a traditional timing analysis approach may not be truly critical in reality. In this paper, we propose using a statistical delay evaluation framework for estimating the quality of a path set. Based upon the new framework, we demonstrate how the traditional definition of a critical path set may deviate from the true critical path set in the deep sub-micron domain. To remedy the problem, we discuss improvements to the existing path selection strategies by including new objectives. We then compare statistical approaches with traditional approaches based upon experimental analysis of both defect-free and defect-injected cases.

For the channel estimation in the pilot channel aided CDMA systems which can support a multi-code scheme, we consider a linear prediction using both pilot and traffic channels. After deriving a new form of the optimal Wiener filter which requires less computational load, for its practical implementation, we propose the decision-directed adaptive linear prediction filter (DD-ALPF). To prevent from falling into the false lock, the proposed DD-ALPF uses the conventional channel estimate obtained only from pilot channel as a baseline for checking the reliability of the filter output. It will be shown through computer simulation that the proposed method can improve the receiver performance and performs better in the fast fading environments, compared with the existing ones.

As the CMOS technology enters the very deep submicron era, inter-wire coupling capacitance becomes the dominant part of load capacitance. The coupling effects have brought new challenges to routing algorithms on both delay estimation and optimization. In this paper, we propose a timing-driven global routing algorithm with consideration of coupling effects. Our two-phase algorithm based on timing-relax method includes a heuristic Steiner tree algorithm to guarantee the timing performance of the initial solution and an optimization algorithm based on coupling-effect-transference. Experimental results are given to demonstrate the efficiency and accuracy of the algorithm.

This Letter presents a novel VQ-based digital image watermarking method. By modifying the conventional GLA algorithm, a codeword-labeled codebook is first generated. Each input image block is then reconstructed by the nearest codeword whose label is equal to the watermark bit. The watermark extraction can be performed blindly. Simulation results show that the proposed method is robust to JPEG compression, vector quantization (VQ) compression and some spatial-domain processing operations.

We propose an efficient algorithm for making multi-layered neural networks (MLN) fault-tolerant to all multiple weight faults in a multi-dimensional interval by injecting intentionally two extreme multi-dimensional values in the interval into the weights of the selected multiple links in a learning phase. The degree of fault-tolerance to a multiple weight fault is measured by the number of essential multiple links. First, we analytically discuss how to choose effectively the multiple links to be injected, and present a learning algorithm for making MLNs fault tolerant to all multiple (i.e., simultaneous) faults in the interval defined by two multi-dimensional extreme points. Then it is proved that after the learning algorithm successfully finishes, MLNs become fault tolerant to all multiple faults in the interval. It is also shown that the time in a weight modification cycle depends little on multiplicity of faults k for small k. These are confirmed by simulation.

Two operations, polynomial multiplication and modular reduction, are newly induced by the properties of the modified Booth's algorithm and irreducible all one polynomials, respectively. A new and effective methodology is hereby proposed for computing multiplication over a class of fields GF(2m) using the two operations. Then a low complexity multiplexer-based multiplier is presented based on the aforementioned methodology. Our multiplier consists of m 2-input AND gates, an (m2 + 3m - 4)/2 2-input XOR gates, and m(m - 1)/2 4 1 multiplexers. For the detailed estimation of the complexity of our multiplier, we will expand this argument into the transistor count, using a standard CMOS VLSI realization. The compared results show that our work is advantageous in terms of circuit complexity and requires less delay time compared to previously reported multipliers. Moreover, our architecture is very regular, modular and therefore, well-suited for VLSI implementation.

In this paper, we present the results of a comparative analysis of Atomic Broadcast algorithms. The analysis was done by using an analytical method to compare the performance of five different classes of Atomic Broadcast algorithms. The five classes of Atomic Broadcast algorithms are determined by the mechanisms used by the algorithms to define the delivery order. To evaluate the performance of algorithms, the analysis relies on contention-aware metrics to provide a measure for both their latency and their throughput. The results thus obtained yield interesting insight into the performance tradeoffs of different Atomic Broadcast algorithms, thus providing helpful information to algorithms and systems designers.

One of the important topics of watermarking technique is a robustness against geometrical transformations. In the previous schemes, a template matching is performed or an additional signal is embedded for the recovery of a synchronization loss. However, the former requires the original template, and the latter degrades the quality of image because both a watermark and a synchronization signal must be embedded. In the proposed scheme only a synchronization signal is embedded for the recovery of both a watermark and a synchronization loss. Then the embedded information depends on the distance between two embedded signal positions. The distance is not changed seriously by random geometrical transformations like StirMark attack unless the embedded signal is disturbed. Therefore, a watermark can be extracted correctly from such geometrically transformed image if the synchronization signal can be recovered.

This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the circuit-delay variation, so it is important to characterize each gate-delay variation accurately. Every transistor in a gate affects transient characteristics of the gate, so it is indispensable to consider an intra-gate variability for the modeling of gate-delay variation. This effect is not captured in a statistical delay analysis reported so far. Our model considers the intra-gate variability by sensitivity constants. We evaluate our modeling accuracy, and we show some simulated results of a circuit delay variation.

In this paper, the absorbing property of the discrete Green's function ABC, which was based on a powerful concept of the TLM method, has been improved by relocating loss process from the time domain to the space domain. The proposed scheme simply adds a loss matrix to the connection matrix in the basic TLM algorithm to make the formulation of the ABC more efficient. Various lengths of absorbing layers discretized for a WR-90 empty waveguide have been tested in terms of reflection property. An expression for an optimum absorbing property has been also derived with respect to the length of the layer. Comparison of the layer with the discrete Green's function ABC shows that the layer in this study has improved reflection property better than approximately 3 and 6 dB, respectively, when 50Δ and 60Δ absorbing layers have been adopted for the WR-90 waveguide. Finally, the layer has been applied to a WR-75 metal insert filter as an example.

This paper reports the design and fabrication of a miniaturized superconducting microstrip line filter using YBCO film on MgO. The filter's resonators are shaped in a double spiral, and the size of the resonators is optimized from the standpoint of the unloaded Q-factor. The 15-pole bandpass filter that has the center frequency of 1.95 GHz and the bandwidth of 20 MHz is designed in the size of 9.7 44 mm. The simulated S-parameter characteristics of the filter is corresponding to the initial design parameters. We fabricated the filter on an MgO substrate with a diameter of 2 inches. The filter had very sharp cutoff and a very low insertion loss of 0.14 dB.