This paper studies a video storage problem that occurs in Video-on-Demand (VOD) networks and in other distributed database systems. Videos should be stored in order to respect various constraints, especially available storage and transmission capacities. We show there exists an algorithm to solve this combinatorial problem through a pricing mechanism and that it converges to a solution under some general conditions. Simulation results with up to 43-node networks and up to 300 videos show that the algorithm is fast.

Some undetectable stuck-at faults called the redundant faults are included in practical combinational circuits. The redundant fault does not affect the functional behavior of the circuit even if it exists. The redundant fault, however, causes undesirable effects to the circuit such as increase of delay time and decrease of testability of the circuit. It is considered that some redundant faults may cause the logical defects in the future. In this paper, firstly, we study the testability of the redundant fault in the combinational circuit by using delay effects. Secondly, we propose a method for generating a test-pair of a redundant fault by using an extended seven-valued calculus, called TGRF (Test-pair Generation for Redundant Fault). TGRF generates a dynamically sensitizable path for the target line which propagates the change in the value on the target line to a primary output. Finally, we show experimental results on the benchmark circuits under the assumptions of the unit delay and the fanout weighted delay models. It shows that test-pairs for some redundant faults are generated theoretically.

This paper describes the new α-particle induced soft error mechanism, the Minority Carrier Outflow (MCO) effect, which may seriously affect the reliability of the scaled DRAMs with three dimensional capacitors. The MCO chargge increases as the device size miniaturizes because of the three dimensional capacitor effect as below. As the device scales down, the storage node volume decreases which results in the higher minority carrier density in the storage node and larger outflow charge. Also as the device plan view miniaturizes, the stack capacitor height or trench depth does not scales down or even increases to keep the storage node capacitance, therefore the initially generated minority carrier becomes larger. A simple analytical MCO model is introduced to evaluate the MCO effect quantitatively. The model agrees well with the three dimensional device simulation. The MCO model predicts that the life time of the minority carrier in the storage node strongly affects the MCO charge, however, even when the life time is as small as the order of 100 ps, the MCO effect can be the major soft error mechanism.

This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate a test generation procedure previously proposed and reduce the number of test vectors generated, while higher fault coverage is derived. The first technique proposed in this paper, which is applied at the first phase of test generation, is rules of ordering vector pairs to be analyzed, to derive high fault coverage without repeating the analysis for the same vector pairs. The second one is to generate new vector pairs for undetected faults, instead of random vector pairs. Both techniques are based on the idea that faults close to primary inputs should be detected earlier than close to primary outputs. The third technique proposed here is how to construct vector pairs from one input vector in order to accelerate test generation especially for circuits with many primary inputs and scan flip-flops. Experimental results for bench-mark circuits show the effectiveness of the techniques.

Conformance testing techniques are required for the efficient production of reliable communication protocols. A lot of conformance testing techniques have been developed. However, most of them can only decide whether an implemented protocol conforms to its specification. That is, the exact locations of faults are not determined by them. This paper presents some conditions that enable to find locations of multiple faults, and then proposes a test sequence generation technique under such conditions. The correctness proof and complexity analysis of the proposed technique are also given. The characteristics of this technique are to generate test sequences based on protocol specifications and interim test results, and to find locations of multiple faults in protocol implementations. Although the length of the test sequence generated by the proposed technique is a little longer than the one generated by the previous one, the class to which the proposed technique can be applied is larger than that to which the previous one can be applied.

A method to design one-dimensional cellular arrays to be used as TPG circuits of BIST is described. The interconnections between cells are not limited to adjacent ones but allowed to some neighbors. Completely regular structures that have full-transition coverages for every k-dimensional subspace of state variables are first shown. Then, almost regular arrays which can operate on maximum cycles are derived based on fast parallel implementations of LFSRs.

In the course of the development of the "Hyper Hospital," a novel medical care system constructed in the computerized information network using virtual reality as its human interface, we devised a virtual reality world creating system which allows users to con figure the world interactively. The re-configuration of the virtual world was designed to be carried out without interruptions of activity and the world can continue to exist during the reconfiguration process. This facility comprises an important part of our Hyper Hospital system because one of our major goals of this proposal of the Hyper Hospital is to restore maximum freedom for patients in the medical care system. Discussion was given in the present study with respect to the basic requirements of the system to be realized, including discussions on the permission given to the participants of different levels, and means by which to modify the structure of the virtual world. A preliminary implementation was described following this general consideration. The developed prototype was shown to be practically suitable to the test of our virtual environment applied to realistic medical scenes.

This paper deals with the problems in testing large mixed-signal ICs. To help generating test patterns of these larger mixed-signal circuits for a functional test, a fast fault simulation algorithm and a fault model voltage stuck-at fault" which the algorithm is based on, are proposed. A voltage stuck-at fault is that a signal line sticks its voltage level at a certain constant. Under an assumption that blocks in a circuit are designed as identically current-independent, i.e. their input impedance can be regarded as infinite and their output impedance as zero, fault simulation can be realized by the event driven method and the concurrent method and can detect voltage stuck-at faults. These methods are essential for digital fault simulation and very effective to high speed simulation, although they were impossible for an analog or mixed-signal circuit by a conventional algorithm. Furthermore, the efficiency of the simulation is improved because I/O relation of blocks is approximated to a stepwise linear function. The above techniques and methods make fault simulation for a mixed-signal circuit possible in practical use. Actually, a fault simulator was implemented, then some test circuits were simulated. The simulator is really faster than conventional simulation based on circuit simulation. Next, fault analysis was applied to several bipolar ICs to verify the validity of the fault model voltage stuck-at faults". Analyses of open and short faults between terminals of transistors and resistors show that this fault model has sufficient coverage (more than 50%) to test mixed-signal circuit.

A 3.3 V single power-supply 64 Mb flash memory with a DBL programming scheme has been developed and fabricated with 0.4 µm CMOS technology. 50 ns access time and 256 b erase/programming unit-capacity have been achieved by using hierarchical word- and bit-line structures and DBL programming scheme. Furthermore in order to lower operating voltage the HiCR cell is used. The chip size is 19.3 mm13.3 mm.

There is general trend toward larger chip size and tighter layout due to customer requests of loading more and more functions on single chip. This trend makes yield difficult to be maintained high enough, since larger amount of defects are distributed on such large and tight-ruled chips. To overcome such a situation, RADLYS (RAnDom Logic Yield Simulator) and DD-TEG (Defect Density TEG) have been developed. DD-TEG extracts defect size distribution and its amount automatically, while RADLYS simulates defects on any layout and outputs yield based on the extracted defect size distribution. Critical layout from yield point of view can be found in this procedure. DD-TEG and RADLYS are used as a set of parameter extraction and simulation of the SPICE. In this paper, we introduce these tools and showed two application results. The predicted yield showed a good agreement with the actual yield in the first application (Optical Device A). Critical layout at the Local I/O portion was found in the second application (Random Logic portion of Memory Device B) and the layout was changed based on the RADLYS results.

Retiming is a technique to resynthesize a synchronous sequential circuit by rearranging flip-flops. In view of logic optimization, retiming can potentially derive a circuit which is more simplified and testable because retiming can convert several sequential redundancies into combinational redundancies. Retiming methods proposed before have no guarantee to generate the same output sequences when the circuit start from a specified initial state such as the reset state. If the circuit with a specified initial state must have the same output sequences after retiming, rearrangement of flip-flops should be restricted. This paper presents a retiming method for circuits with a specified initial state so that retimed circuits give the same output sequences of the original circuits for any input sequences. In the proposed method, during the procedure of retiming each flip-flop keeps a value corresponding to the initial state and unification of flip-flops with different value is avoided. Our procedures uses 5-valued logic on gate level implementation to describe and calculate the values of flip-flops. Therefore after optimization using our method, the circuit has completely the same behavior as that of the original. Experimental results for ISCAS'89 benchmark circuits show the method can be used to optimize the circuits as well as a method without considering the initial state. And testability of the retimed circuit is more enhanced than that of the original circuit.

This paper describes analytical results of high-Tc superconducting asymmetric coplanar strip lines using the frequency-dependent finite-difference time-domain method. The propagation constants of the YBa2Cu3O7-x asymmetric coplanar strip line fabricated on the LiNbO3 substrate are reported. The effect of the SiO2 buffer layer is also investigated.

In this paper, we evaluate the performance of handoff schemes in microcellular personal communication systems (PCS) which cater to both pedestrian and vehicular users. Various performance parameters, including blocking of new calls,channel utilization, handoff blocking and call termination probabilities for each user type are evaluated. We study different queuing disciplines for handoff calls and their impact on system performance. We also study the tradeoff in handoff blocking and call termination probabilities between user types as the handoff traffic carried by the system from each user type is varied.

In this paper we present a design method for all-pass networks with consideration of the stability. It is based on the eigen filter method and Remez exchange algorithm is used to obtain the equiripple phase error solution. In the iteration of the proposed algorithm, the eigen values besides maximum eigen value are used in order to obtain a stable all-pass networks.

Mobile communications have been developing rapidly in recent years. In Japan, a new digital cellular system and digital trunked radio system were introduced. Soon a new personal communication system and road information system will be introduced. Other than those systems, many new mobile communication systems are being developed. These are new pager systems, future public land mobile communication systems, wireless card system and anti-collision radar system etc.

An adaptive joint-process IIR filter with generalized lattice structure is constructed. This filter can borrow both FIR and IIR features and simultaneously holds the well-known merits of lattice structure.

A single bridging fault location technique for CMOS combinational circuits is proposed. In this technique, the cause of an error observed at the primary outputs in deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is [the number of gates][the number of tests]2 bits, which is much smaller than that of the fault dictionary. The experimental results show that the number of possible bridging faults is reduced to less than 5 in several seconds, when using the tests to detect single stuck-at faults and considering only the bridging faults between physically adjacent nets.

A new concept for a navigation and communication satellite system has been proposed. The navigation satellite system that forms the basis of the proposed system has been studied by one of the authors and extended to add a mobile communication function to the system. The satellite system consists of 15 satellites in quasi-geostationary orbit (QGEO) that have a geostationary altitude and high inclination and provide global coverage and positioning capability to the observer through only reception of the range measurement signals generated at the satellites, which are in the same configuration as the satellites in Global Positioning System (GPS), Three satellites out of the 15 satellite are designated to install a subsystem for mobile satellite communication in order to satisfy mobile communication convenience as required in a Future Air Navigation System's (FANS) concept of International Civil Aviation Organization (ICAO). The case studies of 15-satellites constellations demonstrate not only an acceptable positioning accuracy over the whole globe, but also an accuracy distribution weighted on the north pole region as an example of a weighted accuracy distribution. The addition of a mobile communication function suggests a unified system of satellite navigation and communication, which might provide convenience for the civil aviation industry, because the two functions currently depend on different systems.

The advance of mobile network and radio techniques has been rapidly expanding the service area for mobile terminals. Thus, mobile communications have been devoted to the improvement of terminal mobility (TM). Recently, the personal mobility (PM) concept appeared which gives a freedom to use personal telecommunication numbers at any terminal. Therefore, mobile network must next enable a user to access telecommunication services with his/her personal telecommunication number from any terminal at any geographic location. In other words, the mobile network must implement universal mobility (UM) that integrates TM and PM. This paper first provides a definition of UM. Next, it describes the identity and number configurations for UM and then presents network techniques for UM, i.e., the network architecture and UM management procedures. It also presents the current status of standardization on UM in the Personal Digital Cellular system (PDC) and Future Public Land Mobile Telecommunication Systems (FPLMTS).

The dynamics of an artificial neural network derived from a biological system, and its two applications to engineering problems are examined. The model has a multi-layer structure simulating the primary and secondary components in the olfactory system. The basic element in each layer is an oscillator which simulates the interactions between excitatory and inhibitory local neuron populations. Chaotic dynamics emerges from interactions within and between the layers, which are connected to each other by feedforward and feedback lines with distributed delays. A set of electroencephalogram (EEG) obtained from mammalian olfactory system yields aperiodic oscillation with 1/f characteristics in its FFT power spectrum. The EEG also reveals abrupt state transitions between a basal and an activated state. The activated state with each inhalation consists of a burst of oscillation at a common time-varying instantaneous frequency that is spatially amplitude-modulated (AM). The spatial pattern of the activated state seems to represent the class of the input ot the system, which simulates the input from sensory receptors. The KIII model of the olfactory system yields sustained aperiodic oscillation with "1/f" spectrum by adjustment of its parameters. Input in the form of a spatially distributed step funciton induces a state transition to an activated state. This property gives the model its utility in pattern classification. Four different methods (SD, RMS, PCA and FFT) were applied to extract AM patterns of the common output wave forms of the model. The pattern classification capability of the model was evaluated, and synchronization of the output wave form was shown to be crucial in PCA and FFT methods. This synchronization has also been suggested to have an important role in biological systems related to the information extraction by spatiotemporal integration of the output of a transmitting area of cortex by a receiving area.