This paper proposes a semi-autonomous frame synchronization scheme for a TDMA (Time Division Multiple Access)-TDD (Time Division Duplexing) personal communication system to realize accurate frame synchronization in a simple manner. The proposed scheme selects specific adjacent base stations by the station indicator (SID), carries out high resolution frame timing control, and compensates the propagation delay between base stations by using geographical data. This autonomously synchronizes all base stations to each other. Computer simulation and analysis results confirm the accurate and stable TDMA frame synchronization of all base stations even in fading environments.

A new frequency hopped spread spectrum system is introduced. The frequency hopped signal is a combination of multi frequency and multi phase signals and is referred to as Frequency Hopped/Joint Frequency-Phase Modulation (FH/JFPM). A noncoherent receiver for the FH/JFPM signals is introduced and an exact expression for the bit error rate is obtained. A performance analysis of this system is given in the presence of broadband and partial-band noise jamming. The optimal jamming strategy is evaluated. The results show that under these jamming conditions the FH/JFPM perform better than the FH/M-ary DPSK and FH/M-ary FSK systems. It is also shown that for a given channel bandwidth and data rate, the FH/JFPM system has more processing gain than its FSK or DPSK counterparts.

The Institute for Posts and Telecommunications Policy (IPTP) held its first character recognition competition in 1992 to ascertain the present status of ongoing research in character recognition and to find promising algorithms for handwritten numerals. In this paper, we report and analyze the results of this competition. In the competition, we adopted 3-digit handwritten postal code images gathered from live mail as recognition objects. Prior to the competition, 2,500 samples (7,500 characters) were distributed to the participants as traning data. By using about 10,000 different samples (29,883 characters), we tested 13 recognition programs submitted by five universities and eight manufacturing companies. According to the four kinds of evaluation criteria: recognition accuracy, recognition speed, robustness against degradation, and theroretical originality, we selected the best three recognition algorithms as the Prize of Highest Excellence. Interestingly enough, the best three recognition algorithms showed considerable diversity in their methodologies and had very few commonly substituted or rejected patterns. We analyzed the causes for these commonly substituted or rejected patterns and, moreover, examined the human ability to discriminate between these patterns. Next, by considering the complementary characteristics of each recognition algorithm, we studied a multi-expert recognition strategy using the best three recognition algorithms. Three kinds of combination rules: voting on the first candidate rule, minimal sum of candidate order rule, and minimal sum of dissimilarities rule were examined, and the latter two rules decreased the substitution rate to one third of that obtained by one-expert in the competition. Furthermore, we proposed a candidate appearance likelihood method which utilizes the conditional probability of each of ten digits given the candidate combination obtained by each algorithm. From the experiments, this method achieved surprisingly low values of both substitution and rejection rates. By taking account of its learning ability, the candidate appearance likelihood method is considered one of the most promising multi-expert systems.

In this letter, we compare the three compound methods of the Multiple-scale technique to improve the quality of the scale values estimated by the method of fuzzy categories. The results show that the maximum compound method brings higher ability to estimate the scale values than the other methods despite categories used in the scale.

This paper shows that when a pattern matching method used in optical character readers is highly accurate, it can be used effectively in on-line Japanese character recognition. Stroke matching methods used in previous conventional on-line character recognition have restricted the number and the order of strokes. On the other hand, orientation-feature pattern matching methods avoid these restrictions. The authors have improved a pattern matching method with the development in the flexible pattern matching (FPM) method, based on nonlinear shape normalization and nonlinear pattern matching, which includes the normalization-cooperative feature extraction (NCFE) method. These improvements have increased the recognition rate from 81.9% to 95.9%, when applied to the off-line database ETL-9 from the Electrotechnical Laboratory, Japan. When applied on-line to the examination of 151,533 Kanji and Hiragana characters in 3,036 categories, the recognition rate achieved 94.0%, while the cumulative recognition rate within the best ten candidates was 99.1%.

We apply neural networks to implement a line shape recognition/classification system. The purpose of employing neural networks is to eliminate target-specific algorithms from the system and to simplify the system. The system needs only to be trained by samples. The shapes are captured by the following operations. Lines to be processed are segmented at inflection points. Each segment is extended from both ends of it in a certain percentage. The shape of each extended segment is captured as an approximate curvature. Curvature sequence is normalized by size in order to get a scale-invariant measure. Feeding this normalized curvature date to a neural network leads to position-, rotation-, and scale-invariant line shape recognition. According to our experiments, almost 100% recognition rates are achieved against 5% random modification and 50%-200% scaling. The experimental results show that our method is effective. In addition, since this method captures shape locally, partial lines (caused by overlapping etc.) can also be recognized.

In this paper, we propose DSVMA (Data Steal into Voice Multiple Access) scheme for integration of voice and data in wireless information networks. By using speech activity detectors and effective downstream control signals, DSVMA enables data terminals to transmit multi-packet messages when voice terminals are in silent periods. The S-G (throughput versus offered load) performance of the DSVMA system and the blocking probabilities of both the second generation systems and the DSVMA systems are evaluated by the static analysis. A dynamic analysis of a system with finite number of terminals is also presented using an approximate Markov analysis method. Some numerical examples are given in the paper. As a result, it is shown that DSVMA can improve the channel utility efficiency of a circuit-switched TDMA (Time Division Multiple Access) wireless communication system and is directly applicable for second generation wireless information systems.

It is demonstrated that the enhancement in the functional capability of an elemental transistor is quite essential in developing human-like intelligent electronic systems. For this purpose we have introduced the concept of four-terminal devices. Four-terminal devices have an additional dimension in the degree of freedom in controlling currents as compared to the three-terminal devices like bipolar and MOS transistors. The importance of the four-terminal device concept is demonstrated taking the neuron MOS transistor (abbreviated as neuMOS or νMOS) and its circuit applications as examples. We have found that any Boolean functin can be realized by a two-stage configuratin of νMOS inverters. In addition, the variable threshold nature of the device allows us to build real-time reconfigurable logic circuits (no floating gate charging effect is involved in varying the threshold). Based on the principle, we have developed Soft-Hardware Logic Circuits and Real-Time Rule-Variable Data Matching Circuits. A winner-take-all circuit which finds the largest signal by hardware parallel processing has been also developed. The circuit is applied to building an associative memory which is different from Hopfield network in both principle and operation. The hardware algorithm in which binary, multivalue, and analog operations are merged at a very device level is quite essential to establish intelligent information processing systems based on highly flexible, real-time programmable hardwares realized by four-terminal devices.

This paper proposes a group demodulator that employs multi-symbol chirp Fourier transform to demodulate pulse shaped and time asynchronous signals without degradation; this is not possible with conventional group demodulators based on chirp Fourier transform. Computer simulation results show that the bit error rate degradation of the proposed group demodulator at BER=10-3 is less than 0.3dB even when a root Nyquist (α=0.5) filter is used as the transmission pulse shaping filter and the symbol timing offset between the desired channel and the chirp sweep is half the symbol period.

This paper proposes a new fully-digitalized π/4-shift QPSK modulator consisting of a digital pulse shaping filter and a baseband quadrature modulator. By employing a novel digital filter configuration, the required filter memory is reduced to just 6.25% of the conventional one. Moreover, since the proposed baseband modulation scheme does not employ analog mixers or an analog 90 divider, a very accurate, high-stable and compact modulator is realized. It is shown that the proposed scheme achieves excellent low power consumption characteristics and is more suitable for digital LSIC implementation of personal communication terminals than a direct RF modulation scheme and an analog IF modulation scheme.

The paper describes the architecture and the simulated performances of a memory-based chip that emulates human cortical processing in early visual tasks, such as texture segregation. The featural elements present in an image are extracted by a convolution block and subsequently processed by the cortical chip, whose neurons, organized into three layers, gain relational descriptions (intelligent processing) through recurrent inhibitory/excitatory interactions between both inter-and intra-layer parallel pathways. The digital implementation of this architecuture directly maps the set of equations determining the status of the cortical network to achieve an optimal exploitation of VLSI technology in neural computation. Neurons are mapped into a memory matrix whose elements are updated through a programmable computational unit that implements synaptic interconnections. By using 0.5 µm-CMOS technology, full cortical image processing can be attained on a single chip (2020 mm2 die) at a rate higher than 70 frames/second, for images of 256256 pixels.

This paper presents a low-power 8-valued cellular array VLSI for high-speed image processing based on logical neighborhood operations with 33 windows. This array is useful for performing low-level image processing such as noise removal and edge detection, in intelligent integrated systems where immediate response to input change as well as high throughput is needed. In order to achieve high-speed image processing, template matching for neighborhood operations can be performed in parallel on each row. Each row of the image is operated in a pipelining manner. The direct 8-valued encoding of the matched results for three different 33 masks makes it possible to reduce the number of operations by one-third. In the hardware implementation, the matching cell for logical neighborhood operations can be implemented compactly using MOS transistors with different threshold voltage, which are programmed by multiple ion implants. Moreover, a new literal circuit for detecting multiple-valued signals using a dynamic design style eliminates hazards due to timing skews in the difference of various input voltage levels, so that the dynamic power dissipation of the proposed circuit is greatly reduced. Finally, it is demonstrated that the processing time of the proposed cellular array is reduced to about 40 percent in comparison with that of a corresponding binary circuit when power dissipation/area = 0.3 W/100 mm2.

In this paper we propose a method for increasing the reliability in multiprocessor realization of lowpass and highpass FIR digital filters possessing a maximally flat magnitude response. This method is based on the use of array realization of the filter which has been proposed earlier by the authors. It is shown that if a processing module of the array functions erroneously, it is possible to exclude the module and still obtain a lowpass FIR filter. However, as a price we should tolerate a slight degradation in the magnitude response of the filter that is equivalent to a wider transition band. We also analyze the behavior of the filter when our proposed schemes are implemented on more than one module. The justification of our approach is based on that a slight degradation of the spectral characteristics of a filter may be well tolerated in most filtering applications and thus a graceful degradation in the frequency domain can sufficiently reduce the vulnerability to errors.

Stored channel simulation for mobile radio channel can be the common base of the development of future world wide personal radio communication systems, especially for high bit-rate digital system. This paper proposes a mobile radio channel database which is suitable for the laboratory channel simulation using a simple stored channel simulator, also proposed by the author. The database enables the establishment of a mobile radio channel database containing worldwide channel data in a few discs of compact disc.

In robot vision system, enormously large computation power is required to perform three-dimensional (3-D) instrumentation and object recognition. However, many kinds of complex and irregular operations are required to make accurate 3-D instrumentation and object recognition in the conventional method for software implementation. In this paper, a VLSI-oriented Model-Based Robot Vision (MBRV) processor is proposed for high-speed and accurate 3-D instrumentation and object recognition. An input image is compared with two-dimensional (2-D) silhouette images which are generated from the 3-D object models by means of perspective projection. Because the MBRV algorithm always gives the candidates for the accurate 3-D instrumentation and object recognition result with simple and regular procedures, it is suitable for the implementation of the VLSI processor. Highly parallel architecture is employed in the VLSI processor to reduce the latency between the image acquisition and the output generation of the 3-D instrumentation and object recognition results. As a result, 3-D instrumentation and object recognition can be performed 10000 times faster than a 28.5 MIPS workstation.

An automatic zip code recognition system for Japanese mail is proposed in this paper. It is assumed that a zip code is composed of three numerals and requited to be written in a specified frame. In actual images, however, the three numerals sometimes extend outside the specified frame and are not clearly separated. Considering this situation, the authors devised a system with two stages, the segmentation stage and the recognition stage. The segmentation stage consists of five steps: setting and adjusting of initial areas for numeral images (figures), calculation of the center of gravity of each figure, search for the horizontal and vertical boundaries of each figure, determination of the final area for each figure, and normalization of the figure in each final area. In the recognition stage, the Localized Arc Pattern Method (Arc method) proposed by Yoshimura et al. (1991) is implemented hierarchically; that is, a simple Arc method is applied first to each figure and a more complex one is applied subsequently unless the figure is identified in the first step. In the recognition process, every figure is judged as a numeral or otherwise rejected. The proposed system was applied to a database provided by the Institute for Post and Telecommunications Policy (IPTP). The segmentation algorithm yielded an adequate result. The recognition algorithm yielded scores as high as 90.6% in correct recognition rate and 0.7% in error rate. The best score of the precision index (P-index) specified by the IPTP was as low as 15.7 for the above mentioned IPTP database, while the score for another IPTP database was 16.9.

This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.

The issue about document structure recognition and document understanding is today one of interesting subjects from a viewpoint of practical applications. The research objective is to extract the meaningful data from document images interpretatively and also classify them as the predefined item data automatically. In comparison with the traditional image-processing-based approaches, the knowledge-based approaches, which make use of various knowledge in order to interpret structural/constructive features of documents, have been currently investigated as more flexible and applicable methods. In this paper, we propose a totally integrated paradigm for understanding table-form documents from a viewpoint of the architectural framework.

A fast Newton/LMS algorithm is proposed which uses an efficient inversion technique of input autocorrelation matrix when the periodic pseudo random sequence is used as the reference signal. The number of operations is greatly reduced and the computational results show fast convergence rate and low misadjustment error. And the application of the algorithm to the case of nonperiodic reference signal is described.

An efficient algorithm is presented for solving nonlinear resistive networks. In this algorithm, the techniques of the piecewise-linear homotopy method are introduced to the Katzenelson algorithm, which is known to be globally convergent for a broad class of piecewise-linear resistive networks. The proposed algorithm has the following advantages over the original Katzenelson algorithm. First, it can be applied directly to nonlinear (not piecewise-linear) network equations. Secondly, it can find the accurate solutions of the nonlinear network equations with quadratic convergence. Therefore, accurate solutions can be computed efficiently without the piecewise-linear modeling process. The proposed algorithm is practically more advantageous than the piecewise-linear homotopy method because it is based on the Katzenelson algorithm that is very popular in circuit simulation and has been implemented on several circuit simulators.